SN65LVCP114

www.ti.com

SLLSEA8

– JANUARY 2012

over operating conditions range. All parameters are referenced to package pins (unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

POWER CONSUMPTION

Device power dissipation,

Ports A, B, and C in loopback mode with all 12 channels

1800

2300

mW

loopback mode

active. VOD = LOW

Device power dissipation, normal

Device configured in mux-demux mode with 8 channels active.

1400

1800

mW

mode

VOD = LOW

Device power dissipation, lanes

50

mW

disabled

configuration.

All 12 channels active, VOD = LOW, FAST_SW = HIGH.

Device power dissipation,

1800

2300

mW

standby

over operating conditions range. All parameters are referenced to package pins (unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

POWER CONSUMPTION

Device power dissipation,

Ports A, B, and C in loopback mode with all 12 channels

2500

3150

mW

loopback mode

active. VOD = LOW

Device power dissipation, normal

Device configured in mux-demux mode with 8 channels active.

1800

2500

mW

mode

VOD = LOW

Device power dissipation, lanes

50

mW

disabled

configuration.

All 12 channels active, VOD = LOW, FAST_SW = HIGH.

Device power dissipation,

2500

3150

mW

standby

over operating conditions range. All parameters are referenced to package pins (unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP

(1)

MAX

UNIT

CMOS DC SPECIFICATIONS

High-level input current

80

µA

Low-level input current

-80

µA

CML INPUTS (AINP[3:0], AINN[3:0], BINP[3:0], BINN[3:0], CINP[3:0], CINN[3:0])

Differential input resistance

INx_P to INx_N

100

Ω

Input linear dynamic range

Gain = 0.5

1200

mVpp

Common-mode input voltage

Internally biased

V

SCD11

Input differential to common-mode conversion

100 MHz to 7.1GHz

–25

dB

SDD11

Differential input return loss

100 MHz to 7.1GHz

–10

dB

CML OUTPUTS (AOUTP[3:0], AOUTN[3:0], BOUTP[3:0], BOUTN[3:0], COUTP[3:0], COUTN[3:0])

1200

Output linear dynamic range

600

Output offset voltage

20

K28.5 pattern at 14.2 Gbps,

Common-mode output ripple

10

20

K28.5 pattern at 14.2Gbps, no interconnect loss,

Differential path output ripple

20

Output common mode voltage

See Figure 4

V

Change in steady-state common-mode output

±10

mV

voltage between logic states

Low-to-high propagation delay

200

ps

See Figure 5

High-to-low propagation delay

200

ps

Inter-pair output skew

(2)

All outputs terminated with 100

Ω. See Figure 7

50

ps

(1)

All typical values are at 25

°C and with 2.5-V and 3.3-V supply, unless otherwise noted.

(2)

for Skew Compensation, SLLA323.

Copyright

© 2012, Texas Instruments Incorporated

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