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SN75LVDS83CZQLR Datasheet(PDF) 5 Page - Texas Instruments |
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SN75LVDS83CZQLR Datasheet(HTML) 5 Page - Texas Instruments |
5 / 26 page SN75LVDS83C www.ti.com SLLSE66A – OCTOBER 2010 – REVISED SEPTEMBER 2011 PIN FUNCTIONS PIN I/O DESCRIPTION Y0P, Y0M, Y1P, Differential LVDS data outputs. Y1M, Y2P, Y2M Outputs are high-impedance when SHTDN is pulled low (de-asserted) Differential LVDS Data outputs. Y3P, Y3M LVDS Out Output is high-impedance when SHTDN is pulled low (de-asserted). Note: if the application only requires 18-bit color, this output can be left open. Differential LVDS pixel clock output. CLKP, CLKM Output is high-impedance when SHTDN is pulled low (de-asserted). Data inputs; supports 1.8V to 3.3V input voltage selectable by VDD supply. To connect a graphic source successfully to a display, the bit assignment of D[27:0] is critical (and not necessarily intuitive). D0 – D27 For input bit assignment see Figure 11 to Figure 14 for details. Note: if application only requires 18-bit color, connect unused inputs D5, D10, D11, D16, D17, D23, and D27 to GND. CMOS IN with pulldn CLKIN Input pixel clock; rising or falling clock polarity is selectable by Control input CLKSEL. Device shut down; pull low (de-assert) to shut down the device (low power, resets all registers) and SHTDN high (assert) for normal operation. Selects between rising edge input clock trigger (CLKSEL = VIH and falling edge input clock trigger CLKSEL (CLKSEL = VIL). VCC 3.3V digital supply voltage IOVCC I/O supply reference voltage (1.8V up to 3.3V matching the GPU data output signal swing) PLLVCC Power Supply(1) 3.3V PLL analog supply LVDSVCC 3.3V LVDS output analog supply GND Supply ground for VCC, IOVCC, LVDSVCC, and PLLVCC. (1) For a multilayer pcb, it is recommended to keep one common GND layer underneath the device and connect all ground terminals directly to this plane. Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Link(s): SN75LVDS83C |
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