TLV320DAC3203

SLOS756 – MAY 2012

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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

DESCRIPTION (CONTINUED)

Combined with the advanced PowerTune technology, the device can cover operations from 8kHz mono voice

playback to stereo 192kHz DAC playback, making it ideal for portable battery-powered audio and telephony

applications.

The playback path offers signal processing blocks for filtering and effects, true differential output signal, flexible

mixing of DAC and analog input signals as well as programmable volume controls. The TLV320DAC3203

contains two high-power output drivers which can be configured in multiple ways, including stereo and mono

BTL. The integrated PowerTune technology allows the device to be tuned to just the right power-performance

trade-off. Mobile applications frequently have multiple use cases requiring very low-power operation while being

used in a mobile environment. When used in a docked environment, power consumption typically is less of a

concern and lowest possible noise is more important. With PowerTune the TLV320DAC3203 can address both

cases.

The voltage supply range for the TLV320DAC3203 for analog is 1.5V–1.95V, and for digital it is 1.26V–1.95V. To

ease system-level design, a low-dropout regulator (LDO) is integrated to generate the appropriate analog supply

from input voltages ranging from 1.8V to 3.6V. Digital I/O voltages are supported in the range of 1.1V–3.6V.

The required internal clock of the TLV320DAC3203 can be derived from multiple sources, including the MCLK,

BCLK, GPIO pins or the output of internal PLL, where the input to the PLL again can be derived from the MCLK,

BCLK or GPIO pins. Although using the internal, fractional PLL ensures the availability of a suitable clock signal,

it is not recommended for the lowest power settings. The PLL is highly programmable and can accept available

input clocks in the range of 512kHz to 50MHz.

The device is available in the 4mm × 4mm QFN and 2.7mm × 2.7mm WCSP package.

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