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LT6202 Datasheet(PDF) 5 Page - Linear Technology |
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LT6202 Datasheet(HTML) 5 Page - Linear Technology |
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5 / 24 page  LTC2369-18 5 236918fa ADC TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS tSCKL SCK Low Time l 4ns tSSDISCK SDI Setup Time From SCK↑ (Note 11) l 4ns tHSDISCK SDI Hold Time From SCK↑ (Note 11) l 1ns tSCKCH SCK Period in Chain Mode tSCKCH = tSSDISCK + tDSDO (Note 11) l 13.5 ns tDSDO SDO Data Valid Delay from SCK↑ CL = 20pF (Note 11) l 9.5 ns tHSDO SDO Data Remains Valid Delay from SCK↑ CL = 20pF (Note 10) l 1ns tDSDOBUSYL SDO Data Valid Delay from BUSY↓ CL = 20pF (Note 10) l 5ns tEN Bus Enable Time After RDL↓ (Note 11) l 16 ns tDIS Bus Relinquish Time After RDL↑ (Note 11) l 13 ns Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may effect device reliability and lifetime. Note 2: All voltage values are with respect to ground. Note 3: When these pin voltages are taken below ground or above REF or OVDD, they will be clamped by internal diodes. This product can handle input currents up to 100mA below ground or above REF or OVDD without latch-up. Note 4: VDD = 2.5V, OVDD = 2.5V, REF = 5V, fSMPL = 1.6MHz. Note 5: Recommended operating conditions. Note 6: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note 7: Zero-scale error is the offset voltage measured from 0.5LSB when the output code flickers between 00 0000 0000 0000 0000 and 00 0000 0000 0000 0001. Full-scale error is the deviation of the last code transition from ideal and includes the effect of offset error. Note 8: All specifications in dB are referred to a full-scale 5V input with a 5V reference voltage. Note 9: fSMPL = 1.6MHz, IREF varies proportionately with sample rate. Note 10: Guaranteed by design, not subject to test. Note 11: Parameter tested and guaranteed at OVDD = 1.71V, OVDD = 2.5V and OVDD = 5.25V. Note 12: tSCK of 10ns maximum allows a shift clock frequency up to 100MHz for rising capture. Figure 1. Voltage Levels for Timing Specifications 0.8*OVDD 0.2*OVDD 50% 50% 236918 F01 0.2*OVDD 0.8*OVDD 0.2*OVDD 0.8*OVDD tDELAY tWIDTH tDELAY |
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