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EN29LV320C Datasheet(HTML) 17 Page - Eon Silicon Solution Inc.

Part No. EN29LV320C
Description  32 Megabit (4096K x 8-bit / 2048K x 16-bit) Flash Memory Boot Sector Flash Memory, CMOS 3.0 Volt-only
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Maker  EON [Eon Silicon Solution Inc.]
Homepage  http://www.essi.com.tw
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EN29LV320C Datasheet(HTML) 17 Page - Eon Silicon Solution Inc.

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This Data Sheet may be revised by subsequent versions
© 2004 Eon Silicon Solution, Inc.,
www.eonssi.com
or modifications due to changes in technical specifications.
17
EN29LV320C
Rev. B, Issue Date: 2011/05/13
Hardware Data protection
The command sequence requirement of unlock cycles for programming or erasing provides data
protection against inadvertent writes as seen in the Command Definitions table. Additionally, the
following hardware data protection measures prevent accidental erasure or programming, which might
otherwise be caused by false system level signals during Vcc power up and power down transitions, or
from system noise.
SECURED SILICON SECTOR
The EN29LV320C features an OTP memory region where the system may access through a command
sequence to create a permanent part identification as so called Electronic Serial Number (ESN) in the
device. Once this region is programmed and then locked by writing the Secured Silicon Sector Lock
command (refer to Table 5 on page 10), any further modification in the region is impossible. The
secured silicon sector is 128 words in length, and the Secured Silicon Sector Lock Bit (DQ0) is used to
indicate whether the Secured Silicon Sector is locked or not.
The system accesses the Secured Silicon Sector through a command sequence (refer to “Enter
Secured Silicon/ Exit Secured Silicon Sector command Sequence which are in Table 12 on page 18).
After the system has written the Enter Secured Silicon Sector command sequence, it may read the
Secured Silicon Sector by using the address normally occupied by the last sector SA70 (for
EN29LV320CT) or first sector SA0 (for EN29LV320CB). Once entry the Secured Silicon Sector the
operation of boot sectors and main sectors are disabled, the system must write Exit Secured Silicon
Sector command sequence to return to read and write within the remainder of the array. This mode of
operation continues until the system issues the Exit Secured Silicon Sector command sequence, or
until power is removed from the device. On power-up, or following a hardware reset, the device reverts
to sending command to sector SA0.
Low V
B
CCB Write Inhibit
When Vcc is less than V
B
LKO
B
, the device does not accept any write cycles. This protects data during Vcc
power up and power down. The command register and all internal program/erase circuits are disabled,
and the device resets. Subsequent writes are ignored until Vcc is greater than V
B
LKO
B
. The system must
provide the proper signals to the control pins to prevent unintentional writes when Vcc is greater than
V
B
LKO
B
.
Write Pulse “Glitch” protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# = V
B
IL
B
, CE# = V
B
IH
B
, or WE# = V
B
IH
B
. To initiate a write
cycle, CE# and WE# must be a logical zero while OE# is a logical one. If CE#, WE#, and OE# are all
logical zero (not recommended usage), it will be considered a read.
Power-up Write Inhibit
During power-up, the device automatically resets to READ mode and locks out write cycles. Even with
CE# = V
B
IL
B
, WE#= V
B
IL
B
and OE# = V
B
IH
B
, the device will not accept commands on the rising edge of WE#.


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