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EN29LV320C Datasheet(PDF) 22 Page - Eon Silicon Solution Inc.

Part # EN29LV320C
Description  32 Megabit (4096K x 8-bit / 2048K x 16-bit) Flash Memory Boot Sector Flash Memory, CMOS 3.0 Volt-only
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Manufacturer  EON [Eon Silicon Solution Inc.]
Direct Link  http://www.essi.com.tw
Logo EON - Eon Silicon Solution Inc.

EN29LV320C Datasheet(HTML) 22 Page - Eon Silicon Solution Inc.

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This Data Sheet may be revised by subsequent versions
© 2004 Eon Silicon Solution, Inc.,
www.eonssi.com
or modifications due to changes in technical specifications.
22
EN29LV320C
Rev. B, Issue Date: 2011/05/13
The flowchart for DATA# Polling (DQ7) is shown on Flowchart 5. The DATA# Polling (DQ7) timing
diagram is shown in Figure 6.
RY/BY#: Ready/Busy Status output
The RY/BY# is a dedicated, open-drain output pin that indicates whether an Embedded Algorithm is in
progress or completed. The RY/BY# status is valid after the rising edge of the final WE# pulse in the
command sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can be tied together
in parallel with a pull-up resistor to Vcc.
In the output-low period, signifying Busy, the device is actively erasing or programming. This includes
programming in the Erase Suspend mode. If the output is high, signifying the Ready, the device is
ready to read array data (including during the Erase Suspend mode), or is in the standby mode.
DQ6: Toggle Bit I
The EN29LV320C provides a “Toggle Bit” on DQ6 to indicate the status of the embedded programming
and erase operations. (See Table 10)
During an embedded Program or Erase operation, successive attempts to read data from the device at
any address (by active OE# or CE#) will result in DQ6 toggling between “zero” and “one”. Once the
embedded Program or Erase operation is completed, DQ6 will stop toggling and valid data will be read
on the next successive attempts. During Programming, the Toggle Bit is valid after the rising edge of
the fourth WE# pulse in the four-cycle sequence. During Erase operation, the Toggle Bit is valid after
the rising edge of the sixth WE# pulse for sector erase or chip erase.
In embedded programming, if the sector being written to is protected, DQ6 will toggles for about 2
μs,
then stop toggling without the data in the sector having changed. In Sector Erase or Chip Erase, if all
selected sectors are protected, DQ6 will toggle for about 100
μs. The chip will then return to the read
mode without changing data in all protected sectors.
The flowchart for the Toggle Bit (DQ6) is shown in Flowchart 6. The Toggle Bit timing diagram is shown
in Figure 7.
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit.
Under these conditions DQ5 produces a “1.” This is a failure condition that indicates the program or
erase cycle was not successfully completed. Since it is possible that DQ5 can become a 1 when the
device has successfully completed its operation and has returned to read mode, the user must check
again to see if the DQ6 is toggling after detecting a “1” on DQ5.
The DQ5 failure condition may appear if the system tries to program a “1” to a location that is previously
programmed to “0.” Only an erase operation can change a “0” back to a “1.” Under this condition,
the device halts the operation, and when the operation has exceeded the timing limits, DQ5 produces a
“1.” Under both these conditions, the system must issue the reset command to return the device to
reading array data.
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the output on DQ3 can be checked to determine
whether or not an erase operation has begun. (The sector erase timer does not apply to the chip erase
command.) When sector erase starts, DQ3 switches from “0” to “1”. This device does not support
multiple sector erase (continuous sector erase) command sequences so it is not very meaningful since
it immediately shows as a “1” after the first 30h command. Future devices may support this feature.


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