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SP233ECP Datasheet(PDF) 6 Page - Sipex Corporation |
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SP233ECP Datasheet(HTML) 6 Page - Sipex Corporation |
6 / 15 page Rev. 06/20/02 SP202E Series High Performance RS232 Transceivers © Copyright 2002 Sipex Corporation 6 VCC = +5V –5V –5V +5V VSS Storage Capacitor VDD Storage Capacitor C1 C2 C3 C4 + + ++ – – – – Figure 4. Charge Pump — Phase 1 Figure 5. Charge Pump — Phase 2 VCC = +5V –10V VSS Storage Capacitor VDD Storage Capacitor C1 C2 C3 C4 + + ++ – – – – In actual system applications, it is quite possible for signals to be applied to the receiver inputs before power is applied to the receiver circuitry. This occurs, for example, when a PC user attempts to print, only to realize the printer wasn’t turned on. In this case an RS-232 signal from the PC will appear on the receiver input at the printer. When the printer power is turned on, the receiver will operate normally. All of these enhanced devices are fully protected. Charge Pump The charge pump is a Sipex–patented design (5,306,954) and uses a unique approach com- pared to older less–efficient designs. The charge pump still requires four external capacitors, but uses a four–phase voltage shifting technique to attain symmetrical 10V power supplies. There is a free–running oscillator that controls the four phases of the voltage shifting. A description of each phase follows. Phase 1 — V SS charge storage —During this phase of the clock cycle, the positive side of capacitors C 1 and C2 are initially charged to +5V. Cl + is then switched to ground and the charge in C 1 – is transferred to C 2 –. Since C 2 + is connected to +5V, the voltage potential across capacitor C 2 is now 10V. Phase 2 — V SS transfer — Phase two of the clock con- nects the negative terminal of C 2 to the VSS storage capacitor and the positive terminal of C 2 to ground, and transfers the generated –l0V to C 3. Simultaneously, the positive side of capaci- tor C 1 is switched to +5V and the negative side is connected to ground. Phase 3 — V DD charge storage — The third phase of the clock is identical to the first phase — the charge transferred in C 1 produces –5V in the negative terminal of C 1, which is applied to the negative side of capacitor C 2. Since C2 + is at +5V, the voltage potential across C 2 is l0V. Phase 4 — V DD transfer — The fourth phase of the clock connects the negative terminal of C 2 to ground, and transfers the generated l0V across C 2 to C4, the V DD storage capacitor. Again, simultaneously with this, the positive side of capacitor C 1 is switched to +5V and the negative side is con- nected to ground, and the cycle begins again. Since both V+ and V– are separately generated from V CC; in a no–load condition V + and V– will |
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