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SP674BB Datasheet(PDF) 6 Page - Sipex Corporation |
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SP674BB Datasheet(HTML) 6 Page - Sipex Corporation |
6 / 15 page SP574B/674B/1674B/774B 12–Bit Sampling A/D Converters © Copyright 2000 Sipex Corporation 6 SAMPLE–AND–HOLD FUNCTION Although there is no sample–and–hold circuit in the classical sense, the sampling nature of the capacitive DAC makes the SPx74B appear to have a built–in sample–and–hold. The sample–and– hold function of the CDAC architecture is opti- mized to provide full Nyquist sampling at any maximum sampling rate. Because the S/H func- tion is included in the ADC circuitry, the majority of the S/H specifications are included within the A/ D specifications. Note that some system architectures may use an external sample–and–hold. The built–in S/H func- tion of the SPx74B will provide additional isola- tion. Once the internal sample is taken by the CDAC capacitance, the input of the SPx74B is disconnected from the input. This prevents tran- sients occurring during conversion from being inflicted upon the attached buffer. All other 574/ 674–type circuits will cause a transient load cur- rent on the input which will upset the buffer output and may add error to the conversion itself. In addition, the isolation of the input after the acqui- sition time in the SPx74B allows you the opportu- nity to release the HOLD on an external sample– and–hold and start it tracking the next sample. This will increase system throughput with your existing components. When using an external S/H, the SPx74B acts as any other 574–type device because the internal S/ H is transparent. The sample/hold function in the SPx74B is inherent to the capacitor DAC struc- ture, and its timing characteristics are determined by the internally generated clock. However, for multiplexer operation, the internal S/H may elimi- nate the need for an external S/H. The operation of the S/H function is internal to the SPx74B and is USING THE SPX74B SERIES Typical Interface Circuit The SPx74B is a complete A/D converter that is fully operational when powered up and issued a Start Convert Signal. Only a few external compo- nents are necessary. The SPx74B Series have four standard input ranges: 0V to +10V, 0V to +20V, ±5Vand±10V.Figure2depictsatypicalinterface circuit for operating the SPx74B in a unipolar input mode. Figure 3 depicts a typical interface circuit for operating the SPx74B in a bipolar input mode. Further information is given in the follow- ing sections on these connections, but first a few considerations concerning board layout to achieve the best operation. For each application of this device, strict attention must be given to power supply decoupling, board layout (to reduce pickup between analog and digi- tal sections), and grounding. Digital timing, cali- bration and the analog signal source must be considered for correct operation. To achieve specified accuracy, a double–sided printed circuit board with a copper ground plane on the component side is recommended. Keep analog signal traces away from digital lines. It is best to lay the PC board out such that there is an analog section and a digital section with a single point ground connection between the two through an RF bead. If this is not possible, run analog controlled through the normal R/C control line (refer to Figure 1). When the R/C line makes a negative transition, the SPx74B starts the timing of the sampling and conversion. The first two clock cycles are allocated to signal acquisition of the input by the CDAC (this time is defined as t ACQ). Following these two cycles, the input sample is taken and held. The A/D conversion follows this cycle with the duration controlled by the internal clock cycle, which is determined by the specific product model. Note that because the sample is taken relative to the R/C transition, t ACQ is also the traditional “aperture delay” of this internal sample and hold. Since t ACQ is measured in clock cycles, its duration will vary with the internal clock fre- quency. Offset, gain and linearity errors of the S/H circuit, as well as the effects of its droop rate, are included in the overall specs for the SPx74B. R/C CE WAIT FOR CONVERT SIGNAL WAIT FOR BUS READ CONVERSION VIN CDAC VOLTAGE 0 VOLTS t(ACQ) ACQUISITION TIME ACQUISITION TIME = APERTURE DELAY TIME = 0.12 x tCONVERT Figure 1. Sample–and–Hold Function |
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