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SL4019B Datasheet(PDF) 1 Page - System Logic Semiconductor |
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SL4019B Datasheet(HTML) 1 Page - System Logic Semiconductor |
1 / 4 page SL4019B System Logic Semiconductor SLS Quad AND/OR Select Gate High-Voltage Silicon-Gate CMOS The SL4019B types consist of four AND/OR select gate configurations, each consisting of two 2-input AND gates driving a single 2-input gate. Selection is accomplished by control bits Sa and Sb .In addition to selection of either channel A or channel B information, the control bits can be applied simultaneously to accomplish the logical A + B function • Operating Voltage Range: 3.0 to 18 V • Maximum input current of 1 µA at 18 V over full package- temperature range; 100 nA at 18 V and 25 °C • Noise margin (over full package temperature range): 1.0 V min @ 5.0 V supply 2.0 V min @ 10.0 V supply 2.5 V min @ 15.0 V supply ORDERING INFORMATION SL4019BN Plastic SL4019BD SOIC TA = -55 ° to 125° C for all packages LOGIC DIAGRAM PIN 16 =VCC PIN 8 = GND PIN ASSIGNMENT FUNCTION TABLE Inputs Outputs Sa Sb A B Y H L H X H H L L X L L H X H H L H X L L L L X X L H H L L L H H L H H H H H L H H H H H H |
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