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DS1683S+T Datasheet(PDF) 7 Page - Maxim Integrated Products |
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DS1683S+T Datasheet(HTML) 7 Page - Maxim Integrated Products |
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7 / 21 page  7 DS1683 Total-Elapsed-Time and Event Recorder with Alarm On the falling edge of the EVENT signal, the contents of the ETC SRAM counter are written to the ETC shadowed EEPROM registers. When the EVENT pin is low, the ETC register can be written by the I2C bus. For example, when it comes time to reset the time stored in the ETC register, an I2C write command can be issued to set all the bits to 0. ETC Alarm Register The ETC Alarm register is a 32-bit value and contains the value that is compared to the accumulated ETC value. When a nonzero value is programmed into the ETC Alarm register, the ETC alarm function is enabled and the DS1683 compares the value in the ETC SRAM counter with the programmed value in the ETC Alarm register. When the ETC SRAM Counter matches or exceeds the alarm value, the ETC alarm flag (ETC AF) is set. Note: To disable the ETC alarm function, program the ETC Alarm register to a value of all 0s. An alarm value of all 0s disables the ETC alarm function. Event Counter Register This 16-bit Event Counter stores the number of falling edges seen on the EVENT pin. Once the Event Counter reaches a value of FFFFh, event counting stops. The Event Counter register is backed by four banks of shad- owed EEPROM, which allow for 200k+ write cycles occur before a wearout condition. When an I2C read occurs when the EVENT pin is high, a snapshot of the value from the Event Counter SRAM is made available for the I2C bus. When the EVENT pin is logic 0, I2C reads take data from the shadowed EEPROM Event Counter bank memory. On POR, the Event Counter value stored in shadowed EEPROM bank memory is loaded into the Event Counter SRAM location. This also happens when a low-to-high transition occurs on the EVENT pin, or when an I2C write to the Event Counter register occurs. When data is writ- ten to the Event Counter register, the value is stored in the shadowed EEPROM bank memory, and also in the corresponding Event Counter SRAM location. This data is transferred after the STOP of the I2C command. On the falling edge of the EVENT signal, the Event Counter SRAM register is incremented by a value of one, and the contents of the Event Counter SRAM are written to the Event Counter shadowed EEPROM. When the EVENT pin is low, the Event Counter register can be written by the I2C bus. For example, when it comes time to reset the accumulated number of events in the Event Counter register, an I2C write command can be issued to set all of the bits to 0. Event Counter Alarm Register The Event Counter Alarm register is a 16-bit register, and contains the value that is compared to the accumulated Event Counter value. When a nonzero value is programmed into the Event Counter Alarm register, the Event Counter alarm function is enabled, and the DS1683 compares the value in the Event Counter SRAM with the programmed value in the EVENT Alarm register. When the Event Counter SRAM value matches or exceeds the alarm value, the Event Counter alarm flag (EVENT AF) is set. Note: To disable the Event Counter alarm function, pro- gram the Event Counter Alarm register to a value of all 0s. An alarm value of all 0s disables the Event Counter alarm function. Alarm Output The ALARM pin is an open-drain structure, and set- ting the alarm polarity bit (ALRM POL) located in the Configuration register determines if the ALARM output is active high or active low (default is active low). The DS1683 monitors the values in the ETC and Event Counter registers and compares them to the values in the ETC and Event Counter Alarm registers. When the ETC and Event Counter values match or exceed their corre- sponding alarm values, their alarm flags (EVENT AF and ETC AF, located in the Status register) are set to a value of 1, indicating an alarm condition. If the correspond- ing Enable bits (ETC ALRM EN and EVENT ALRM EN, located in the Configuration register) are active, then the ALARM output is driven to its active state and is latched. Once the alarm condition has been cleared, the cor- responding alarm flag (EVENT AF and/or ETC AF) automatically clears. Once the actual alarm condition is cleared, the CLR ALM bit must be used to clear an active ALARM pin state. If the alarm condition is still present when the CLR ALM bit is toggled, the ALARM simply reactivates and latches. |
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