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AD9518-0ABCPZ Datasheet(PDF) 6 Page - Analog Devices |
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AD9518-0ABCPZ Datasheet(HTML) 6 Page - Analog Devices |
6 / 64 page AD9518-0 Data Sheet Rev. C | Page 6 of 64 CLOCK INPUTS Table 3. Parameter Min Typ Max Unit Test Conditions/Comments CLOCK INPUTS (CLK, CLK) Differential input Input Frequency 01 2.4 GHz High frequency distribution (VCO divider) 01 1.6 GHz Distribution only (VCO divider bypassed) Input Sensitivity, Differential 150 mV p-p Measured at 2.4 GHz; jitter performance is improved with slew rates > 1 V/ns Input Level, Differential 2 V p-p Larger voltage swings may turn on the protection diodes and may degrade jitter performance Input Common-Mode Voltage, VCM 1.3 1.57 1.8 V Self-biased; enables ac coupling Input Common-Mode Range, VCMR 1.3 1.8 V With 200 mV p-p signal applied; dc-coupled Input Sensitivity, Single-Ended 150 mV p-p CLK ac-coupled; CLK ac-bypassed to RF ground Input Resistance 3.9 4.7 5.7 kΩ Self-biased Input Capacitance 2 pF 1 Below about 1 MHz, the input should be dc-coupled. Care should be taken to match VCM. CLOCK OUTPUTS Table 4. Parameter Min Typ Max Unit Test Conditions/Comments LVPECL CLOCK OUTPUTS Termination = 50 Ω to VS − 2 V OUT0, OUT1, OUT2, OUT3, OUT4, OUT5 Differential (OUT, OUT) Output Frequency, Maximum 2950 MHz Using direct to output; see Figure 16 for peak-to-peak differential amplitude Output High Voltage (VOH) VS_LVPECL − 1.12 VS_LVPECL − 0.98 VS_LVPECL − 0.84 V Output Low Voltage (VOL) VS_LVPECL − 2.03 VS_LVPECL − 1.77 VS_LVPECL − 1.49 V Output Differential Voltage (VOD) 550 790 980 mV This is VOH − VOL for each leg of a differential pair for default amplitude setting with driver not toggling; the peak-to-peak amplitude measured using a differential probe across the differential pair with the driver toggling is roughly 2× these values (see Figure 16 for variation over frequency) TIMING CHARACTERISTICS Table 5. Parameter Min Typ Max Unit Test Conditions/Comments LVPECL Termination = 50 Ω to VS − 2 V; level = 810 mV Output Rise Time, tRP 70 180 ps 20% to 80%, measured differentially Output Fall Time, tFP 70 180 ps 80% to 20%, measured differentially PROPAGATION DELAY, tPECL, CLK-TO-LVPECL OUTPUT High Frequency Clock Distribution Configuration 835 995 1180 ps See Figure 28 Clock Distribution Configuration 773 933 1090 ps See Figure 30 Variation with Temperature 0.8 ps/°C OUTPUT SKEW, LVPECL OUTPUTS1 LVPECL Outputs That Share the Same Divider 5 15 ps LVPECL Outputs on Different Dividers 13 40 ps All LVPECL Outputs Across Multiple Parts 220 ps 1 This is the difference between any two similar delay paths while operating at the same voltage and temperature. |
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