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AD9518-4ABCPZ-RL7 Datasheet(PDF) 4 Page - Analog Devices |
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AD9518-4ABCPZ-RL7 Datasheet(HTML) 4 Page - Analog Devices |
4 / 64 page AD9518-4 Data Sheet Rev. B | Page 4 of 64 SPECIFICATIONS Typical values are given for VS = VS_LVPECL = 3.3 V ± 5%; VS ≤ VCP ≤ 5.25 V; TA = 25°C; RSET = 4.12 kΩ; CPRSET = 5.1 kΩ, unless otherwise noted. Minimum and maximum values are given over full VS and TA (−40°C to +85°C) variation. POWER SUPPLY REQUIREMENTS Table 1. Parameter Min Typ Max Unit Test Conditions/Comments VS 3.135 3.3 3.465 V 3.3 V ± 5% VS_LVPECL 2.375 VS V Nominally 2.5 V to 3.3 V ± 5% VCP VS 5.25 V Nominally 3.3 V to 5.0 V ± 5% RSET Pin Resistor 4.12 kΩ Sets internal biasing currents; connect to ground CPRSET Pin Resistor 2.7 5.1 10 kΩ Sets internal CP current range, nominally 4.8 mA (CP_lsb = 600 μA); actual current can be calculated by CP_lsb = 3.06/CPRSET; connect to ground BYPASS Pin Capacitor 220 nF Bypass for internal LDO regulator; necessary for LDO stability; connect to ground PLL CHARACTERISTICS Table 2. Parameter Min Typ Max Unit Test Conditions/Comments VCO (ON-CHIP) Frequency Range 1450 1800 MHz See Figure 11 VCO Gain (KVCO) 50 MHz/V See Figure 6 Tuning Voltage (VT) 0.5 VCP − 0.5 V VCP ≤ VS when using internal VCO; outside of this range, the CP spurs may increase due to CP up/down mismatch Frequency Pushing (Open-Loop) 1 MHz/V Phase Noise at 100 kHz Offset −109 dBc/Hz f = 1625 MHz Phase Noise at 1 MHz Offset −128 dBc/Hz f = 1625 MHz REFERENCE INPUTS Differential Mode (REFIN, REFIN) Differential mode (can accommodate single-ended input by ac grounding undriven input) Input Frequency 0 250 MHz Frequencies below about 1 MHz should be dc-coupled; be careful to match VCM (self-bias voltage) Input Sensitivity 250 mV p-p PLL figure of merit (FOM) increases with increasing slew rate (see Figure 10); the input sensitivity is sufficient for ac-coupled LVPECL and LVDS signals Self-Bias Voltage, REFIN 1.35 1.60 1.75 V Self-bias voltage of REFIN1 Self-Bias Voltage, REFIN 1.30 1.50 1.60 V Self-bias voltage of REFIN1 Input Resistance, REFIN 4.0 4.8 5.9 kΩ Self-biased1 Input Resistance, REFIN 4.4 5.3 6.4 kΩ Self-biased1 Dual Single-Ended Mode (REF1, REF2) Two single-ended CMOS-compatible inputs Input Frequency (AC-Coupled) 20 250 MHz Slew rate > 50 V/μs Input Frequency (DC-Coupled) 0 250 MHz Slew rate > 50 V/μs; CMOS levels Input Sensitivity (AC-Coupled) 0.8 V p-p Should not exceed VS p-p Input Logic High 2.0 V Input Logic Low 0.8 V Input Current −100 +100 μA Pulse Width High/Low 1.8 ns This value determines the allowable input duty cycle and is the amount of time that a square wave is high/low Input Capacitance 2 pF Each pin, REFIN/REFIN (REF1/REF2) PHASE/FREQUENCY DETECTOR (PFD) PFD Input Frequency 100 MHz Antibacklash pulse width = 1.3 ns, 2.9 ns 45 MHz Antibacklash pulse width = 6.0 ns Antibacklash Pulse Width 1.3 ns Register 0x017[1:0] = 01b 2.9 ns Register 0x017[1:0] = 00b; Register 0x017[1:0] = 11b 6.0 ns Register 0x017[1:0] = 10b |
Similar Part No. - AD9518-4ABCPZ-RL7 |
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Similar Description - AD9518-4ABCPZ-RL7 |
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