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Si4777-A20-GM Datasheet(PDF) 8 Page - Silicon Laboratories |
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Si4777-A20-GM Datasheet(HTML) 8 Page - Silicon Laboratories |
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8 / 54 page  Si4770/77-A20 8 Rev. 0.9 Figure 2. Digital Zero-IF I/Q Table 4. Digital Zero-IF I/Q Interface Characteristics (Si4777 Only)1 (TAMB = –40 to 85 °C, VA = 4.5 to 5.5 V, VD = 2.7 to 3.6 V, VIO1 = 1.7 to 3.6 V, VIO2 = 1.2 to 3.6 V) Parameter Symbol Test Condition Min Typ Max Unit IQCLK Output Cycle Time tCYC:IQCLK 0.8 x per per2 1.2 x per ns IQCLK Output Pulse Width High tHI:IQCLK 0.22 x per — 0.59 x per ns IQCLK Output Pulse Width Low tLO:IQCLK 0.41 x per — 0.78 x per ns IQFS Output Delay tPD:IQFS 0 — (0.5 x per) + 18 ns IQFS Output Setup to IQCLK Rise3 tSU:IQFS (0.5 x per) – 18 — — ns IOUT Output Delay tPD:IOUT 0 — (0.5 x per) + 18 ns QOUT Output Delay tPD:QOUT 0 — (0.5 x per) + 18 ns IOUT Output Setup to IQCLK rise3 tSU:IOUT (0.5 x per) – 18 — — ns QOUT Output Setup to IQCLK Rise3 tSU:QOUT (0.5 x per) – 18 — — ns Notes: 1. Guaranteed by characterization. 2. per is the IQCLK I/Q bit clock period. Refer to Table 15 on page 35 for IQCLK bit clock frequencies. 3. Minimum time the Si4770/77-A20 will produce between valid output and the next rising edge of IQCLK IQCLK out IQFS out tCYC:IQCLK Max tCYC:IQCLK Min tHI:IQCLK MIN tLO:IQCLK MAX tHI:IQCLK MAX tLO:IQCLK MIN tPD:IQFS MAX tPD:IQFS MIN tSU:IQFS IOUT out tPD:IOUT MAX tPD:IOUT MIN tSU:IOUT QOUT out tPD:QOUT MAX tPD:QOUT MIN tSU:QOUT |
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