t

(BUF)

t

(HDSTA)

t

(LOW)

t

R

t

F

t

(HDDAT)

t

(HIGH)

t

(SUSTA)

t

(SUDAT)

t

(HDSTA)

t

(SUSTO)

SCL

SDA

P

S

S

P

ADS1000-Q1

www.ti.com

SBAS480A – SEPTEMBER 2009 – REVISED AUGUST 2010

Table 1. Timing Diagram Definitions

FAST MODE

HIGH-SPEED MODE

PARAMETER

MIN

MAX

MIN

MAX

UNITS

SCLK operating frequency

0.4

3.4

MHz

Bus free time between STOP and START

600

160

ns

conditions

Hold time after repeated START condition

600

160

ns

After this period, the first clock is generated.

Repeated START condition setup time

600

160

ns

STOP condition setup time

600

160

ns

Data hold time

0

0

ns

Data setup time

100

10

ns

SCLK clock low period

1300

160

ns

SCLK clock high period

600

60

ns

Clock/data fall time

300

160

ns

Clock/data rise time

300

160

ns

or an A1 within the orderable name.

The ADS1000 responds to General Call Reset, which is an address byte of 00h followed by a data byte of 06h.

The ADS1000 acknowledges both bytes.

On receiving a General Call Reset, the ADS1000 performs a full internal reset, just as though it had been

powered off and then on. If a conversion is in process, it is interrupted; the output register is set to zero, and the

configuration register returns to its default setting.

The ADS1000 always acknowledges the General Call address byte of 00h, but it does not acknowledge any

General Call data bytes other than 04h or 06h.

Fast, which allows a clock frequency of up to 400kHz; and High-speed mode (also called Hs mode), which allows

a clock frequency of up to 3.4MHz. The ADS1000 is fully compatible with all three modes.

No special action needs to be taken to use the ADS1000 in Standard or Fast modes, but High-speed mode must

be activated. To activate High-speed mode, send a special address byte of 00001XXX following the start

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