Frame1:I CSlaveAddressByte

2

Frame2:OutputRegisterUpperByte

StartBy

Master

ACKBy

ADS1000

ACKBy

Master

From

ADS1000

From

ADS1000

1

9

1

9

···

···

···

···

SDA

SCL

SDA

(Continued)

SCL

(Continued)

1

0

0

1

A2

A1

A0

R/W

D15

D14

D13

D12

D11

D10

D9

D8

Frame3:OutputRegisterLowerByte

Frame4:ConfigurationRegister

(Optional)

ACKBy

Master

StopBy

Master

ACKBy

Master

From

ADS1000

1

9

1

D7

D6

D5

D4

D3

D2

D1

D0

ST/

BSY

0

0

SC

0

0

PGA1 PGA0

9

ADS1000-Q1

www.ti.com

SBAS480A – SEPTEMBER 2009 – REVISED AUGUST 2010

Bits 1 - 0: PGA

Bits 1 and 0 control the ADS1000 gain setting; see Table 4.

Table 4. PGA Bits

PGA1

PGA0

GAIN

0

1

2

1

0

4

1

1

8

(1) Default setting

READING FROM THE ADS1000

A user can read the output register and the contents of the configuration register from the ADS1000. To do this,

address the ADS1000 for reading, and read three bytes from the device. The first two bytes are the output

register contents; the third byte is the configuration register contents.

A user does not always have to read three bytes from the ADS1000. If only the contents of the output register

are needed, read only two bytes.

Reading more than three bytes from the ADS1000 has no effect. All of the bytes beginning with the fourth byte

will be FFh. See Figure 7 for a timing diagram of an ADS1000 read operation.

WRITING TO THE ADS1000

A user can write new contents into the configuration register (the contents of the output register cannot change).

To do this, address the ADS1000 for writing, and write one byte to it. This byte is written into the configuration

register.

Writing more than one byte to the ADS1000 has no effect. The ADS1000 ignores any bytes sent to it after the

first one, and will only acknowledge the first byte. See Figure 8 for a timing diagram of an ADS1000 write

operation.

Figure 7. Timing Diagram for Reading from the ADS1000

Copyright © 2009–2010, Texas Instruments Incorporated

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Product Folder Link(s): ADS1000-Q1