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BQ76PL536A-Q1 Datasheet(PDF) 3 Page - Texas Instruments |
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BQ76PL536A-Q1 Datasheet(HTML) 3 Page - Texas Instruments |
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3 / 55 page  bq76PL536A-Q1 www.ti.com SLUSAM3 – MAY 2011 PIN TYPE(1) DESCRIPTION NAME NO. BAT2 64 P Power-supply voltage, connect to most-positive cell +, tie to BAT1 on PCB CB1 12 O Cell-balance control output CB2 10 O Cell-balance control output CB3 8 O Cell-balance control output CB4 6 O Cell-balance control output CB5 4 O Cell-balance control output CB6 2 O Cell-balance control output CONV_H 36 I Host-to-device interface – initiates a synchronous conversion. Pin has 250-nA internal sink to VSS. CONV_N 59 OD Current-mode output to the next-higher bq76PL536A-Q1 to initiate a conversion CONV_S 21 I Input from the adjacent lower bq76PL536A-Q1 to initiate a conversion CS_H 43 I Host-to-device interface – active-low chip select from host. Internal 100-kΩ pullup resistor CS_N 52 OD Current-mode output used to select the next-higher bq76PL536A-Q1 for SPI communication CS_S 29 I Current-mode input SPI chip-select (slave-select) from the next-lower bq76PL536A-Q1 DRDY_H 37 O Host-to-device interface – conversion complete, data-ready indication DRDY_N 58 I Current-mode input indicating conversion data is ready from next-higher bq76PL536A-Q1 DRDY_S 22 OD Current-mode output indicating conversion data is ready to the next lower bq76PL536A-Q1 FAULT_H 39 O Host-to-device interface – FAULT condition detected in this or higher (North) device FAULT_N 56 I Current-mode input indicating a system status change from the next-higher bq76PL536A-Q1 FAULT_S 24 OD Current-mode output GPAI+ 48 AI General-purpose (differential) analog input, connect to VSS if unused. GPAI – 47 AI General-purpose (differential) analog input, connect to VSS if unused. GPIO 45 IOD Digital open-drain I/O. A 10-k Ω to 2-MΩ pullup is recommended. HSEL 44 I Host interface enable, 0 = enable, 1 = disable LDOA 17 P Internal analog 5-V LDO bypass connection, requires 2.2- µF ceramic capacitor for stability LDOD1 18 P Internal digital 5-V LDO bypass connection 1, requires 2.2- µF ceramic capacitor for stability. This pin is tied internally to LDOD2. This pin should be tied to LDOD2 externally. LDOD2 46 P Internal digital 5-V LDO bypass connection 2, requires 2.2- µF ceramic capacitor for stability. This pin is tied internally to LDOD1. This pin should be tied to LDOD1 externally. NC30 30 – No connection NC51 51 – No connect NC62 62 – No connect REG50 32 P 5-V user LDO output, requires 2.2- µF ceramic capacitor for stability SCLK_H 40 I Host-to-device interface – SPI clock from host SCLK_N 55 OD Current-mode output SPI clock to the next-higher bq76PL536A-Q1 SCLK_S 26 I Current-mode input SPI clock from the next-lower bq76PL536A-Q1 SDI_H 42 I Host-to-device interface – data from host to device (host MOSI signal) SDI_N 53 OD Current-mode output for SPI data to the next-higher bq76PL536A-Q1 SDI_S 28 I Current-mode input for SPI data from the next-lower bq76PL536A-Q1 SDO_H 41 O Host-to-device interface – data from device to host (host MISO signal), 3-state pin, 250-nA internal pullup SDO_N 54 I Current-mode input for SPI data from the next-lower bq76PL536A-Q1 SDO_S 27 OD Current-mode output for SPI data to the next-lower bq76PL536A-Q1 TEST 50 I Factory test pin. Connect to VSS in user circuitry. This pin includes ~100-k Ω internal pulldown TS1+ 20 AI Differential temperature sensor input TS1 – 19 AI Differential temperature sensor input TS2+ 61 AI Differential temperature sensor input TS2 – 60 AI Differential temperature sensor input VC0 13 AI Sense-voltage input terminal for negative terminal of first cell (VSS) VC1 11 AI Sense voltage input terminal for positive terminal of the first cell Copyright © 2011, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Link(s): bq76PL536A-Q1 |
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