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bq24272RGER Datasheet(PDF) 5 Page - Texas Instruments |
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bq24272RGER Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 32 page  bq24272 www.ti.com SLUSB09 – JUNE 2012 ELECTRICAL CHARACTERISTICS (continued) Circuit of , VUVLO < VIN < VOVP AND VIN>VBAT+VSLP, TJ = 0°C – 125°C and TJ = 25°C for typical values (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Battery detection current before charge done (sink IDETECT 2.5 mA current) tDETECT Battery detection time 250 ms VIH(CD) CD input high logic level 1.3 V VIL(CD) CD input low logic level 0.4 V INPUT PROTECTION IINLIM = 1.5 A 1.35 1.5 1.65 IINLIM Input current limit VIN=5V, DC current pulled from SW A IINLIM = 2.5 A 2.3 2.5 2.8 Input DPM threshold 4.2 4.76 V VIN_DPM Input DPM accuracy –2% 2% VDRV Internal bias regulator voltage 5 5.2 5.45 V IDRV DRV Output current 10 mA VDO_DRV DRV Dropout voltage (VIN – VDRV) IIN = 1A, VIN = 5V, IDRV = 10mA 450 mV VUVLO IC active threshold voltage VIN rising, 150 mV hysteresis 3.6 3.8 4.0 V VSLP Sleep-mode entry threshold, VIN-VBAT 2.0 V ≤ VBAT ≤ VOREG, VIN falling 0 40 100 mV VSLP_EXIT Sleep-mode exit hysteresis 2.0 V ≤ VBAT ≤ VOREG 40 100 160 mV Deglitch time for supply rising above VSLP+VSLP_EXIT Rising voltage, 2-mV over drive, tRISE=100ns 30 ms VOVP Input supply OVP threshold voltage IN, VIN Rising, 100 mV hysteresis 10.3 10.5 10.7 V 1.025 × 1.05 × 1.075 × VBOVP Battery OVP threshold voltage VBAT threshold over VOREG to turn off charger during charge V VBATREG VBATREG VBATREG % of VBOVP hysteresis Lower limit for VBAT falling from above VBOVP 1 VBATREG VBATUVLO Battery UVLO threshold voltage 2.5 V VIN_DPM – VBAT_SOURCE Bad source detection threshold V 80mV Bad source detection deglitch 32 ms ILIMIT Cycle by cycle current limit 4.1 4.9 5.6 A TSHUTDWN Thermal shutdown 10°C Hysteresis 165 C TREG Thermal regulation threshold 120 C Safety timer accuracy –20% 20% STAT, INT IIH High-level leakage current V/CHG = V/PG = 5 V 1 µA VOL Low-level output saturation voltage IO = 10 mA, sink current 0.4 V PWM CONVERTER Internal top reverse blocking MOSFET on-resistance IIN_LIMIT = 1.5 A, Measured from VIN to PMIDU 45 80 m Ω Internal top N-channel Switching MOSFET on- Measured from PMID to SW 65 110 m Ω resistance Internal bottom N-channel MOSFET on-resistance Measured from SW to PGND 65 115 m Ω fOSC Oscillator frequency 1.35 1.50 1.65 MHz DMAX Maximum duty cycle 95% DMIN Minimum duty cycle 0 BATTERY-PACK NTC MONITOR VHOT High temperature threshold VTS falling, 1%VDRV Hysteresis 29.7 30 30.5 %VDRV VCOLD Low temperature threshold VTS rising, 1%VDRV Hysteresis 59.5 60 60.4 %VDRV TSOFF TS Disable threshold VTS rising, 2%VDRV Hysteresis 70 73 %VDRV tDGL(TS) Deglitch time on TS change 50 ms VIH Input high threshold VPULLUP = 1.8 V, SDA and SCL 1.3 V VIL Input low threshold VPULLUP = 1.8 V, SDA and SCL 0.4 V VOL Output low threshold ISDA = 10 mA, sink current 0.4 V IIH Input high leakage current VPULLUP = 1.8 V, SDA and SCL 1 µA tWATCHDOG Watchdog timer timeout 30 s Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Link(s) :bq24272 |
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