CD74HC4017-Q1

HIGH-SPEED CMOS LOGIC DECADE COUNTER/DIVIDER

WITH 10 DECODED OUTPUTS

SCLS546SA − OCTOBER 2003 − REVISED APRIL 2008

4

POST OFFICE BOX 655303

timing requirements over recommended operating free-air temperature range (unless otherwise

noted) (see Figure 1)

PARAMETER

V

MIN

MAX

UNIT

PARAMETER

MIN

MAX

MIN

MAX

UNIT

2 V

6

4

Maximum clock frequency

4.5 V

30

20

MHz

Maximum clock frequency

6 V

35

23

MHz

2 V

80

120

CP

4.5 V

16

24

t

Pulse duration

CP

6 V

14

20

ns

Pulse duration

2 V

80

120

ns

MR

4.5 V

16

24

MR

6 V

14

20

2 V

75

110

CE to CP

4.5 V

15

22

t

Setup time

CE to CP

6 V

13

19

ns

Setup time

2 V

5

5

ns

MR inactive

4.5 V

5

5

MR inactive

6 V

5

5

2 V

0

0

Hold time, CE to CP

4.5 V

0

0

ns

h

,

6 V

0

0