CDCLVD1208RHDR datasheet(7/21 Pages) TI1

Part #	CDCLVD1208RHDR

Description	2:8 Low Additive Jitter LVDS Buffer

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Manufacturer	TI1 [Texas Instruments]

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CDCLVD1208

www.ti.com

SCAS899 – AUGUST 2010

TYPICAL CHARACTERISTICS

INPUT- AND OUTPUT-CLOCK PHASE NOISES

vs

FREQUENCY FROM the CARRIER

(TA = 25°C and VCC = 2.5V)

Input clock RMS jitter is 32 fs from 10 kHz to 20 MHz and additive RMS jitter is 152 fs

Figure 3. 100 MHz Input and Output Phase Noise Plot

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Product Folder Link(s): CDCLVD1208

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