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CDCLVD1216RGZR Datasheet(PDF) 7 Page - Texas Instruments |
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CDCLVD1216RGZR Datasheet(HTML) 7 Page - Texas Instruments |
7 / 20 page 250 260 270 280 290 300 310 320 330 340 350 0 100 200 300 400 500 600 800 Frequency − MHz 700 T = 25 C A o 2.625V 2.5V 2.375V CDCLVD1216 www.ti.com SCAS900B – OCTOBER 2010 – REVISED JANUARY 2011 TYPICAL CHARACTERISTICS INPUT- AND OUTPUT-CLOCK PHASE NOISES vs FREQUENCY FROM the CARRIER (TA = 25°C and VCC = 2.5V) Input clock RMS jitter is 32 fs from 10 kHz to 20 MHz and additive RMS jitter is 152 fs Figure 3. 100 MHz Input and Output Phase Noise Plot spacer Figure 4. Differential Output Voltage vs Frequency Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Link(s): CDCLVD1216 |
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