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DAC5687-EP Datasheet(PDF) 11 Page - Texas Instruments |
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DAC5687-EP Datasheet(HTML) 11 Page - Texas Instruments |
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11 / 75 page  www.ti.com ELECTRICAL CHARACTERISTICS (DIGITAL SPECIFICATIONS) DAC5687-EP SGLS333 – JUNE 2006 over recommended operating free-air temperature range, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 3.3 V, IOVDD = 3.3 V, DVDD = 1.8 V, IOUT FS = 19.2 mA (unless otherwise noted) DIGITAL SPECIFICATIONS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CMOS INTERFACE VIH High-level input voltage 2 3 V VIL Low-level input voltage 0 0 0.8 V IIH High-level input current –40 40 µA IIL Low-level input current –40 40 µA Input capacitance 5 pF IOVDD – Iload = –100 µA V 0.2 VOH PLLLOCK, SDO, SDIO 0.8 × Iload = –8 mA V IOVDD Iload = 100 µA 0.2 V 0.22 × VOL PLLLOCK, SDO, SDIO Iload = 8 mA IOVD V D External or dual-clock modes 16 250 Input data rate MSPS PLL clock mode 16 160 PLL At 600-kHz offset, measured at DAC output, 133 dBc/Hz 25 MHz 0-dBFS tone, FDATA = 125 MSPS, 4x interpolation, pll_freq = 1, pll_kv = 0 Phase noise At 6-MHz offset, measured at DAC output, 25 MHz 0-dBFS tone, 125 MSPS, 148.5 dBc/Hz 4x interpolation, pll_freq = 1, pll_kv = 0 pll_freq = 0, pll_kv = 0 370 pll_freq = 0, pll_kv = 1 480 VCO maximum frequency MHz pll_freq = 1, pll_kv = 0 495 pll_freq = 1, pll_kv = 1 520 pll_freq = 0, pll_kv = 0 225 pll_freq = 0, pll_kv = 1 200 VCO minimum frequency MHz pll_freq = 1, pll_kv = 0 480 pll_freq = 1, pll_kv = 1 480 NCO and QMC BLOCKS QMC clock rate 320 MHz NCO clock rate 320 MHz SERIAL PORT TIMING Setup time, SDENB to rising edge of ts(SDENB) 20 ns SCLK Setup time, SDIO valid to rising edge ts(SDIO) 10 ns of SCLK Hold time, SDIO valid to rising edge th(SDIO) 5 ns of SCLK tSCLK Period of SCLK 100 ns tSCLKH High time of SCLK 40 ns tSCLK Low time of SCLK 40 ns Data output delay after falling edge of td(Data) 10 ns SCLK 11 Submit Documentation Feedback |
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