SN74LVTH16374EP

3.3V ABT 16BIT EDGETRIGGERED DTYPE FLIPFLOP

WITH 3STATE OUTPUTS

SCBS779A − NOVEMBER 2003 – OCTOBER 2004

2

POST OFFICE BOX 655303

description/ordering information (continued)

A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high

or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive

the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus

lines without need for interface or pullup components.

OE does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while

the outputs are in the high-impedance state.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors

with the bus-hold circuitry is not recommended.

the minimum value of the resistor is determined by the current-sinking capability of the driver.

disables the outputs, preventing damaging current backflow through the device when it is powered down. The

power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,

which prevents driver conflict.

ORDERING INFORMATION

TA

PACKAGE†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

−40

°C to 85°C

TSSOP − DGG

Tape and reel

CLVTH16374IDGGREP

LH16374EP

−40

°C to 85°C

SSOP − DL

Tape and reel

CLVTH16374IDLREP

LH16374EP

† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are

available at www.ti.com/sc/package.

FUNCTION TABLE

(each flip-flop)

INPUTS

OUTPUT

OE

CLK

D

OUTPUT

Q

L

↑

H

H

L

↑

LL

L

H or L

X

Q0

H

X

X

Z

logic diagram (positive logic)

1OE

1CLK

1D1

To Seven Other Channels

1Q1

2OE

2CLK

2D1

2Q1

To Seven Other Channels

1

48

47

24

25

36

C1

1D

13

2

C1

1D