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SN75LVCP601RTJR Datasheet(PDF) 7 Page - Texas Instruments

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Part # SN75LVCP601RTJR
Description  Two-Channel SATA 6-Gb/s Redriver
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

SN75LVCP601RTJR Datasheet(HTML) 7 Page - Texas Instruments

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SN75LVCP601
www.ti.com
SLLSE41B
– JUNE 2010 – REVISED FEBRUARY 2012
2. Auto low-power mode (triggered when a given channel is in the electrically idle state for more than 100
µs
and EN = Vcc)
– The device enters and exits low-power mode by actively monitoring the input signal (VIDp-p) level on
each of its channels independently. When the input signal on either or both channels is in the electrically
idle state, that is, VIDp-p
< 50 mV and stays in this state for >100 µs, the associated channel(s) enters
into the low-power state. In this state, output of the associated channel(s) is driven to VCM and the
device selectively shuts off some circuitry to lower power by
>80% of its normal operating power. Exit
time from the auto low-power mode is
<50 ns.
Out-of-Band (OOB) SUPPORT
The squelch detector circuit within the device enables full detection of OOB signaling as specified in the SATA
specification. Differential signal amplitude at the receiver input of 50 mVpp or less is not detected as an activity
and hence not passed to the output. Differential signal amplitude of 150 mVp-p or more is detected as an activity
and therefore passed to the output, indicating activity. Squelch circuit ON/OFF time is 5 ns, maximum. While in
squelch mode, outputs are held to VCM.
DEVICE POWER
The SN75LVCP601 is designed to operate from a single 3.3 V supply. Always practice proper power-supply
sequencing procedure. Apply Vcc first, before any input signals are applied to the device. The power-down
sequence is in reverse order.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)
VALUE
UNIT
Supply voltage range(2)
VCC
–0.5 to 4
V
Voltage range
Differential I/O
–0.5 to 4
V
Control I/O
–0.5 to Vcc + 0.5
V
Human-body model(3)
±10,000
V
Electrostatic discharge
Charged-device model(4)
±1500
V
Machine model(5)
±200
V
Continuous power dissipation
See Thermal Table
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)
All voltage values, except differential voltages, are with respect to the network ground terminal.
(3)
Tested in accordance with JEDEC Standard 22, Test Method A114-B.
(4)
Tested in accordance with JEDEC Standard 22, Test Method C101-A.
(5)
Tested in accordance with JEDEC Standard 22, Test Method A115-A.
THERMAL INFORMATION
SN75LVCP601
THERMAL METRIC(1)
QFN
UNITS
20 PINS
θJA
Junction-to-ambient thermal resistance(2)
38
°C/W
θJCtop
Junction-to-case (top) thermal resistance(3)
40
°C/W
θJB
Junction-to-board thermal resistance(4)
10
°C/W
(1)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2)
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3)
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4)
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
Copyright
© 2010–2012, Texas Instruments Incorporated
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