VID = 0 V

VOD = 0 V

t PLHD

t PHLD

IN

OUT

ClockInput

0V

VA

VB

1/f

O

PRBSInput

0V

VA

VB

PRBSOutput

0V

VY

VZ

0V

0V

0V

VY–VZ

VY–VZ

VY–VZ

ActualOutput

IdealOutput

1/f

O

PeriodJitter

Cycle-to-CycleJitter

Peak-to-PeakJitter

ActualOutput

tjit(pp)

tc(n)

tc(n)

tc(n+1)

tjit(pp)=|tc(n)-1/f |

O

tjit(cc)=|tc(n)-tc(n+1)|

<3-inch,50-

TL

(7,62cm)

W

<3-inch,50-

TL

(7,62cm)

W

25-inchFR4

(63,5cm)

DC

Block

DC

Block

DC

Block

DC

Block

Coax

Coax

Coax

Coax

D+

D–

Pattern

Generator

400-mV

Differential

PP

Characterization TestBoard

Jitter Test

Instrument

Coupled

TransmissionLine

SMA

SMA

SMA

SMA

SMA

SN65LVCP202

SN65LVCP202

PARAMETER MEASUREMENT INFORMATION (continued)

Figure 6. Propagation Delay Input to Output

A.

All input pulses are supplied by an Agilent 81250 Stimulus System.

B.

The measurement is made on a TEK TDS6604 running TDSJIT3 application software.

Figure 7. Driver Jitter Measurement Waveforms

Figure 8. AC Test Circuit — Jitter and Output Rise Time Test Circuit

The SN65LVCP202 input equalizer provides 5-dB frequency gain to compensate for the frequency loss of a

shorter backplane transmission line. For characterization purposes, a 24-inch (61-cm) FR-4 coupled transmission

line is used in place of the backplane trace. The 24-inch (61-cm) trace provides roughly 5 dB of attenuation

between 375 MHz and 1.875 GHz, representing closely the characteristics of a short backplane trace. The loss

tangent of the FR4 in the test board is 0.018 with an effective

ε(r) of 4.1.

Copyright © 2009, Texas Instruments Incorporated

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