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SN65LVCP402 Datasheet(PDF) 6 Page - Texas Instruments |
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SN65LVCP402 Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 20 page  V ODB(PP) V ODPE(PP) SWITCHING CHARACTERISTICS SN65LVCP402 SLLS699A – JUNE 2007 – REVISED JANUARY 2009....................................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS (continued) over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT Output preemphasis voltage Px_2:Px_1 = 00 0 ratio, Px_2:Px_1 = 01 3 RL = 100 Ω ±1%; V(PE) x = Channel 1 or 2; dB Px_2:Px_1 = 10 6 See Figure 3 Px_2:Px_1= 11 9 Output preemphasis is set to 9 dB during test Preemphasis duration PREx_x = 1; t(PRE) 175 ps measurement Measured with a 100-MHz clock signal; RL = 100 Ω ±1%, See Figure 4 Differential on-chip termination between OUT+ and ro Output resistance 100 Ω OUT– CONTROL INPUTS IIH High-level Input current VIN = VCC 5 µA IIL Low-level Input current VIN = GND -125 -90 µA R(PU) Pullup resistance 35 k Ω POWER CONSUMPTION PD Device power dissipation All outputs terminated 100 Ω 290 414 mW Device power dissipation in PZ All outputs in 3-state 331 mW 3-state All outputs ICC Device current consumption PRBS 27-1 pattern at 4 Gbps 115 mA terminated 100 Ω over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT MULTIPLEXER t(SM) Multiplexer switch time Multiplexer to valid output 3 6 ns DIFFERENTIAL OUTPUTS Low-to-high propagation tPLH 0.5 0.7 ns delay Propagation delay input to output See Figure 6 High-to-low propagation tPHL 0.5 0.7 ns delay tr Rise time 80 ps 20% to 80% of VO(DB); Test Pattern: 100-MHz clock signal; See Figure 5 and Figure 8 tf Fall time 80 ps tsk(p) Pulse skew, | tPHL – tPLH | (2) 20 ps tsk(o) Output skew(3) All outputs terminated with 100 Ω 25 100 ps tsk(pp) Part-to-part skew(4) 300 ps 3-State switch time to tzd Assumes 50 Ω to Vcm and 150 pF load on each output 20 ns disable 3-State switch time to tze Assumes 50 Ω to Vcm and 150 pF load on each output 10 ns enable See Figure 8 for test circuit. RJ Device random jitter, rms BERT setting 10–15 0.8 2 ps-rms Alternating 10-pattern. (1) All typical values are at 25°C and with 3.3 V supply unless otherwise noted. (2) tsk(p) is the magnitude of the time difference between the tPLH and tPHL of any output of a single device. (3) tsk(o) is the magnitude of the time difference between the tPLH and tPHL of any two outputs of a single device. (4) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits. 6 Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): SN65LVCP402 |
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