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TLK110PTR Datasheet(PDF) 7 Page - Texas Instruments |
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TLK110PTR Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 104 page  TLK110 www.ti.com SLLS901A – DECEMBER 2011 – REVISED FEBRUARY 2012 2.7 JTAG Interface PIN TYPE DESCRIPTION NAME NO. JTAG_TCK 8 I, PU JTAG Test Clock: This pin has a weak internal pullup. JTAG_TDI 12 I, PU JTAG Test Data Input: This pin has a weak internal pullup. JTAG_TDO 9 O JTAG Test Data Output JTAG_TMS 10 I, PU JTAG Test Mode Select: This pin has a weak internal pullup. JTAG_TRSTN 11 I, PU JTAG Reset: This pin is an active low asynchronous test reset. This pin has a weak internal pullup. 2.8 Reset and Power Down PIN TYPE DESCRIPTION NAME NO. This pin is an active-low reset input that initializes or re-initializes all the internal registers of the RESETN 29 I, PU TLK110. Asserting this pin low for at least 1 µs will force a reset process to occur. All jumper options are reinitialized as well. . Register access is required for this pin to be configured either as power down or as an interrupt. The default function of this pin is power down. When this pin is configured for a power down function, an active low signal on this pin places the PWR_DNN/INT 7 I, OD, PU device in power down mode. When this pin is configured as an interrupt pin then this pin is asserted low when an interrupt condition occurs. The pin has an open-drain output with a weak internal pull-up. Some applications may require an external pull-up resistor. 2.9 Power and Bias Connections PIN TYPE DESCRIPTION NAME NO. RBIAS 24 I Bias Resistor Connection. Use a 4.87k Ω 1% resistor connected from RBIAS to GND. Power Feedback Output. 10µf and 0.1 μF capacitors (ceramic preferred), should be placed close to PFBOUT 23 O PFBOUT. In single-supply operation, connect this pin to PFBIN1 and PFBIN2 (pin 18 and pin 37). See Figure 3-1 for proper placement In multiple supply operation, this pin is not used. PFBIN1 18 Power Feedback Input. These pins are fed with power from PFBOUT (pin 23) in single supply operation. In multiple supply operation a 1.5V external power should be connected to these pins. A small capacitor I PFBIN2 37 of 0.1µF should be connected close to each pin. The internal linear regulator is powered down by writing to register 0x00d0. VDD33_IO 32, 48 P I/O 3.3V Supply IOGND 35, 47 P I/O ground DGND 36 P Digital ground AVDD33 22 P Analog 3.3V power supply AGND 15, 19 P Analog ground RESERVED 20 I/O RESERVED: This pin must be pulled-up through 2.2 k Ω resistor to AVDD33 supply Copyright © 2011–2012, Texas Instruments Incorporated Pin Descriptions 7 Submit Documentation Feedback Product Folder Link(s): TLK110 |
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