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SM32C6416DGLZ50AEP Datasheet(PDF) 4 Page - Texas Instruments |
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SM32C6416DGLZ50AEP Datasheet(HTML) 4 Page - Texas Instruments |
4 / 93 page 1.4.1 Device Characteristics SM320C6414-EP, SM320C6415-EP, SM320C6416-EP FIXED-POINT DIGITAL SIGNAL PROCESSORS SGUS043D – MAY 2003 – REVISED SEPTEMBER 2008 www.ti.com Table 1-1 provides an overview of the C6414, C6415, and C6416 DSPs. Table 1-1 shows significant features of the C64x devices, including the capacity of on-chip RAM, the peripherals, the CPU frequency, and the package type with pin count. Table 1-1. Characteristics of the C6414, C6415, and C6416 Processors HARDWARE FEATURES C6414, C6415, AND C6416 EMIFA (64-bit bus width) 1 (default clock source = AECLKIN) EMIFB (16-bit bus width) 1 Peripherals (default clock source = BECLKIN) Not all peripherals pins EDMA (64 independent channels) 1 are available at the same HPI (32- or 16-bit user selectable) 1 (HPI16 or HPI32) time. (For more details, see the Device PCI (32-bit) [DeviceID Register value 0xA106] 1 (C6415/C6416 only) Configuration section.) McBSPs 3 (default internal clock source = CPU/4 clock frequency) Peripheral performance is dependent on chip-level UTOPIA (8-bit mode) 1 (C6415/C6416 only) configuration. 32-bit timers 3 (default internal clock source = CPU/8 clock frequency) General-purpose input/output 0 (GP0) 16 VCP 1 (C6416 only) Decoder coprocessors TCP 1 (C6416 only) Size (bytes) 1056K 16K-byte (16KB) L1 program (L1P) cache On-chip memory Organization 16KB L1 data (L1D) cache 1024KB unified mapped RAM/cache (L2) CPU ID + CPU Rev ID Control Status Register (CSR[31:16]) 0x0C01 DEVICE_REV[19:16] Silicon revision Silicon Revision Identification Register 1111 1.03 or earlier Device_ID (DEVICE_REV[19:16]) 0001 1.03 Address: 0x01B0 0200 0010 1.1 Frequency MHz 500 2 ns (C6414-50A, C6415-50A, C6416-50A) Cycle time ns (500-MHz CPU, 100-MHz EMIF)(1) Core (V) 1.25 V (-50A) Voltage I/O (V) 3.3 V PLL options CLKIN frequency multiplier Bypass (x1), x6, x12 BGA package 23 mm × 23 mm 532-pin BGA (GLZ) Process technology CMOS 0.3 µm Product Preview (PP) Product status Advance Information (AI) PD Production Data (PD) (1) On these C64x devices, the rated EMIF speed affects only the SDRAM interface on EMIFA. For more detailed information, see the EMIF Device Speed section of this data manual. Introduction 4 Submit Documentation Feedback |
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