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TMS320DM6433ZDU4 Datasheet(PDF) 1 Page - Texas Instruments |
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TMS320DM6433ZDU4 Datasheet(HTML) 1 Page - Texas Instruments |
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1 / 271 page  1 TMS320DM6433 Digital Media Processor 1.1 Features TMS320DM6433 Digital Media Processor www.ti.com SPRS343C – NOVEMBER 2006 – REVISED JUNE 2008 – 256K-Bit (32K-Byte) L1P Program • High-Performance Digital Media Processor RAM/Cache [Flexible Allocation] (DM6433) – 640K-Bit (80K-Byte) L1D Data RAM/Cache – 2.5-, 2-, 1.67-, 1.51-, 1.43-ns ns Instruction [Flexible Allocation] Cycle Time – 1M-Bit (128K-Byte) L2 Unified Mapped – 400-, 500, -600-, 660-, 700-MHz C64x+™ RAM/Cache [Flexible Allocation] Clock Rate • Supports Little Endian Mode Only – Eight 32-Bit C64x+ Instructions/Cycle – 3200, 4000, 4800, 5280, 5600 MIPS • Video Processing Subsystem (VPSS) – Fully Software-Compatible With C64x – Front End Provides (Resizer Only): – Commercial and Automotive (Q or S suffix) • Resize Images From 1/4x to 4x Grades • Separate Horizontal and Vertical Control – Low-Power Device (L suffix) – Back End Provides: • VelociTI.2™ Extensions to VelociTI™ • Hardware On-Screen Display (OSD) Advanced Very-Long-Instruction-Word (VLIW) • Four 54-MHz DACs for a Combination of TMS320C64x+™ DSP Core – Composite NTSC/PAL Video – Eight Highly Independent Functional Units – Luma/Chroma Separate Video With VelociTI.2 Extensions: (S-video) • Six ALUs (32-/40-Bit), Each Supports – Component (YPbPr or RGB) Video Single 32-Bit, Dual 16-Bit, or Quad 8-Bit (Progressive) Arithmetic per Clock Cycle • Digital Output • Two Multipliers Support Four 16 x 16-Bit – 8-/16-bit YUV or up to 24-Bit RGB Multiplies (32-Bit Results) per Clock – HD Resolution Cycle or Eight 8 x 8-Bit Multiplies (16-Bit – Up to 2 Video Windows Results) per Clock Cycle • External Memory Interfaces (EMIFs) – Load-Store Architecture With Non-Aligned Support – 32-Bit DDR2 SDRAM Memory Controller With 256M-Byte Address Space (1.8-V I/O) – 64 32-Bit General-Purpose Registers • Supports up to 333-MHz (data rate) bus – Instruction Packing Reduces Code Size and interfaces to DDR2-400 SDRAM – All Instructions Conditional – Asynchronous 8-Bit Wide EMIF (EMIFA) – Additional C64x+™ Enhancements With up to 64M-Byte Address Reach • Protected Mode Operation • Flash Memory Interfaces • Exceptions Support for Error Detection – NOR (8-Bit-Wide Data) and Program Redirection – NAND (8-Bit-Wide Data) • Hardware Support for Modulo Loop Auto-Focus Module Operation • Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels) • C64x+ Instruction Set Features • Two 64-Bit General-Purpose Timers (Each – Byte-Addressable (8-/16-/32-/64-Bit Data) Configurable as Two 32-Bit Timers) – 8-Bit Overflow Protection – Bit-Field Extract, Set, Clear • One 64-Bit Watch Dog Timer – Normalization, Saturation, Bit-Counting • One UART With RTS and CTS Flow Control – VelociTI.2 Increased Orthogonality • Master/Slave Inter-Integrated Circuit (I2C – C64x+ Extensions Bus™) • Compact 16-bit Instructions • One Multichannel Buffered Serial Port • Additional Instructions to Support (McBSP0) Complex Multiplies – I2S and TDM • C64x+ L1/L2 Memory Architecture – AC97 Audio Codec Interface Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this document. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Copyright © 2006–2008, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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