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TMS320DM6433ZWT7 Datasheet(PDF) 4 Page - Texas Instruments |
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TMS320DM6433ZWT7 Datasheet(HTML) 4 Page - Texas Instruments |
4 / 271 page 1.3 Functional Block Diagram JTAG Interface System Control PLLs/Clock Generator Input Clock(s) Power/Sleep Controller Pin Multiplexing DSP Subsystem C64x+ t DSP CPU 32 KB L1 Pgm 128 KB L2 RAM 80 KB L1 Data Video Processing Subsystem (VPSS) 10b DAC On-Screen Display (OSD) Video Encoder (VENC) 10b DAC 10b DAC 10b DAC Back End 8b BT.656, Y/C, 24b RGB NTSC/ PAL, S-Video, RGB, YPbPr Switched Central Resource (SCR) Peripherals EDMA I2C UART Serial Interfaces DDR2 Mem Ctlr (32b) Async EMIF/ NAND/ (8b) Program/Data Storage Watchdog Timer PWM System General- Purpose Timer PCI (33 MHz) VLYNQ EMAC With MDIO Connectivity HPI McASP McBSP OSC Boot ROM GPIO Front End Resizer TMS320DM6433 Digital Media Processor SPRS343C – NOVEMBER 2006 – REVISED JUNE 2008 www.ti.com Figure 1-1 shows the functional block diagram of the DM6433 device. Figure 1-1. TMS320DM6433 Functional Block Diagram 4 TMS320DM6433 Digital Media Processor Submit Documentation Feedback |
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