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TPA2054D4YZKR Datasheet(PDF) 6 Page - Texas Instruments |
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TPA2054D4YZKR Datasheet(HTML) 6 Page - Texas Instruments |
6 / 30 page DEVICE RESET OPERATING CHARACTERISTICS TPA2054D4 SLOS607 – APRIL 2009 ..................................................................................................................................................................................................... www.ti.com Figure 3. SCL and SDA Timing Figure 4. Start and Stop Conditions Timing Apply logic low to the RESET pin to deactivate the TPA2054D4 and return all I2C registers to their default state. This clears the LIM_Lock bit to logic low, allowing changes to the headphone output limiter byte. Refer to the Register Map section for a complete list of default states. The I2C registers cannot be programmed until RESET returns to logic high. RESET requires a 1 ms minimum hold time at logic low for a valid reset command. On power-up, ensure that the DVDD and VDDHP voltages have settled and DVDD is at least 1.7V before setting RESET to logic high. The TPA2054D4 activates in soft shutdown mode, SWS bit at logic high. VDD = 3.6 V, TA = 25°C, RSPEAKER = 8 Ω + 33 µH, RHEADPHONES = 16 Ω, Total HP Gain = 6 dB, Total Class-D Gain = 6 dB, MODE[2:0] = 001 (single-ended mode)(unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER AMPLIFIER THD = 1%, VDD = 3.6 V, f = 1 kHz 700 mW PO Speaker output power THD = 10%, VDD = 3.6 V, f = 1 kHz 860 mW THD = 1%, VDD = 4.2 V, f = 1 kHz 940 mW VOS Offset Voltage VDD = 5.5 V –13 5 13 mV Output impedance in shutdown 2 k Ω SNR Signal-to-noise ratio PO = 250 mW; 90 dB En Noise output voltage Total gain = 0 dB; A-weighted 22 µV RMS VDD = 5.0 V, PO = 1 W, f = 1 kHz 0.18 % THD+N Total harmonic distortion plus noise VDD = 3.6 V, PO = 0.6 W, f = 1 kHz 0.25 % 6 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPA2054D4 |
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