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TPS2456A Datasheet(PDF) 2 Page - Texas Instruments |
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TPS2456A Datasheet(HTML) 2 Page - Texas Instruments |
2 / 32 page TPS2456A SLVSBI8 – JULY 2012 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. PRODUCT INFORMATION(1) DEVICE TEMPERATURE PACKAGE MARKING TPS2456ARHH –40°C to 85°C QFN36 (6mm × 6mm) 2456A (1) For package and ordering information see the Package Option Addendum at the end of this document or see the TI Web site at www.ti.com. THERMAL INFORMATION TPS2456A THERMAL METRIC(1) RHH UNITS 36 PINS θJA Junction-to-ambient thermal resistance(2) 32 θJC(top) Junction-to-case(top) thermal resistance (3) 23 θJB Junction-to-board thermal resistance (4) 11 °C/W ψJT Junction-to-top characterization parameter (5) 0.5 ψJB Junction-to-board characterization parameter (6) 10 θJC(bottom) Junction-to-case(bottom) thermal resistance (7) 2.1 SPACER (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. (2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. (3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC- standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. (4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. (5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7). (6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7). Spacer (7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. ABSOLUTE MAXIMUM RATINGS (1) Over recommended junction temperature range and all voltages referenced to GND, unless otherwise noted. VALUE PINS OR PIN GROUPS UNITS MIN MAX GAT1x, GAT2x –0.3 30 V INx, OUTx, SENPx, SENMx, SETx, ENx, FLTx, PGx, ORENx –0.3 20 V CTx, MONx –0.3 5 V FLTx, PGx current sinking 5 mA MONx current sourcing 5 mA VINT current –1 1 mA Human Body Model 2 kV ESD Charged Device Model 0.5 kV Junction Temperature Internally Limited °C (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only. Functional operation of the device under any conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute maximum rated conditions for extended periods of time may affect device reliability. 2 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TPS2456A |
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