TPS54719

SLVSB69 – JUNE 2012

www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

ORDERING INFORMATION

PACKAGE

PART NUMBER

–40°C to 140°C

3 × 3 mm QFN

TPS54719RTE

ABSOLUTE MAXIMUM RATINGS

VALUE

UNIT

MIN

MAX

Input voltage

VIN

–0.3

7

V

EN

–0.3

7

BOOT

PH + 8

VSENSE

–0.3

3

COMP

–0.3

3

PWRGD

–0.3

7

SS/TR

–0.3

3

RT

–0.3

6

Output voltage

BOOT-PH

8

V

PH

–0.6

7

PH 10 ns Transient

–2

7

Source current

EN

100

μA

RT

100

Sink current

COMP

100

μA

PWRGD

10

mA

SS/TR

100

μA

Electrostatic discharge (HBM)

2

kV

Electrostatic discharge (CDM)

500

V

–40

140

°C

–65

150

°C

THERMAL INFORMATION

TPS54719

UNITS

RTE (16 PINS)

Junction-to-ambient thermal resistance (standard board)

49.1

37.0

Junction-to-top characterization parameter

0.7

Junction-to-board characterization parameter

21.8

°C/W

Junction-to-case(top) thermal resistance

50.7

Junction-to-case(bottom) thermal resistance

7.5

Junction-to-board thermal resistance

21.8

(1)

For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(2)

distortion starts to substantially increase. See power dissipation estimate in the application section of this data sheet for more

information.

(3)

Test boards conditions:

(a) 2 inches x 2 inches, 4 layers, thickness: 0.062 inch

(b) 2 oz. copper traces located on the top of the PCB

(c) 2 oz. copper ground planes on the 2 internal layers and bottom layer

(d) 4 thermal vias (10mil) located under the device package

2

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Product Folder Link(s): TPS54719