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ADC1003S030TS Datasheet(PDF) 4 Page - Integrated Device Technology |
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ADC1003S030TS Datasheet(HTML) 4 Page - Integrated Device Technology |
4 / 19 page ADC1003S030_040_050_3 © IDT 2012. All rights reserved. Product data sheet Rev. 03 — 2 July 2012 4 of 19 Integrated Design Technology ADC1003S030/040/050 Single 10 bits ADC, up to 30 MHz, 40 Mhz or 50 MHz, with voltage regulator 7. Pinning information 7.1 Pinning ADC1003S 050TS CLK VCCD1 TC DGND1 VCCA IR AGND D9 DEC D8 RB D7 RM D6 VI D5 RT D4 OE D3 VCCD2 D2 DGND2 D1 VCCO D0 OGND n.c. 014aaa320 1 2 3 4 5 6 7 8 9 10 11 12 13 14 16 15 18 17 20 19 22 21 24 23 26 25 28 27 Fig 2. Pin configuration 7.2 Pin description Table 3. Pin description Symbol Pin Description CLK 1 clock input TC 2 two’s complement input (active LOW) VCCA 3 analog supply voltage (5 V) AGND 4 analog ground DEC 5 decoupling input RB 6 reference voltage BOTTOM input RM 7 reference voltage MIDDLE VI 8 analog input voltage RT 9 reference voltage TOP input OE 10 output enable input (CMOS level input, active LOW) VCCD2 11 digital supply voltage 2 (5 V) DGND2 12 digital ground 2 VCCO 13 supply voltage for output stages (3 V to 5 V) OGND 14 output ground n.c. 15 not connected D0 16 data output; bit 0 (Least Significant Bit (LSB)) D1 17 data output; bit 1 D2 18 data output; bit 2 D3 19 data output; bit 3 |
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