ADC1410S080HN-C1 datasheet(9/38 Pages) IDT | Single 14-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps; CMOS or LVDS DDR digital outputs

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ADC1410S080HN-C1 Datasheet(PDF) 9 Page - Integrated Device Technology

Part #	ADC1410S080HN-C1

Description	Single 14-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps; CMOS or LVDS DDR digital outputs

Download	38 Pages

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Manufacturer	IDT [Integrated Device Technology]

Direct Link	http://www.idt.com

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[1]

Typical values measured at VDDA =3V, VDDO =1.8 V, Tamb =25 C and CL = 5 pF; minimum and maximum values are across the full temperature range Tamb = 40 C to +85 C

at VDDA =3V, VDDO = 1.8 V; VINP  VINM = 1 dBFS; internal reference mode; applied to CMOS and LVDS interface; unless otherwise specified.

10.2 Clock and digital output timing

IMD

Intermodulation

distortion

fi1 = 1.5 MHz;

fi2 =4.5 MHz

-89-

-

89-

-88-

-89

-

dBc

fi1 =28.5MHz;

fi2 =31.5MHz

-88-

-

88-

-88-

-88

-

dBc

fi1 =68.5MHz;

fi2 =71.5MHz

-87-

-

87-

-86-

-86

-

dBc

fi1 = 168.5 MHz;

fi2 =171.5 MHz

-84-

-

85-

-83-

-84

-

dBc

Table 7.

Dynamic characteristics[1] …continued

Symbol

Parameter

Conditions

ADC1410S065

ADC1410S080

ADC1410S105

ADC1410S125

Unit

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Table 8.

Clock input and digital output timing characteristics[1]

Symbol

Parameter

Conditions

ADC1410S065

ADC1410S080

ADC1410S105

ADC1410S125

Unit

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Clock timing input: pins CLKP and CLKM

fclk

clock

frequency

40

-

65

60

-

80

75

-

105

100

-

125 MHz

tlat(data)

data latency

time

-

13.5

-

-

13.5

-

-

13.5

-

-

13.5

-

clock

cycles

clk

clock duty

cycle

DCS_EN = logic 1

30

50

70

30

50

70

30

50

70

30

50

70

%

DCS_EN = logic 0

45

50

55

45

50

55

45

50

55

45

50

55

%

td(s)

sampling

delay time

-0.8

-

-

0.8-

-0.8

-

-

0.8

-

ns

twake

wake-up time

-76-

-

76-

-76-

-76

-

s

CMOS Mode timing output: pins D13 to D0 and DAV

tPD

propagation

delay

DATA

13.6

14.9

16.4

11.9

12.9

14.4

8.0

10.8

12.4

8.2

9.7

11.3 ns

DAV

-

4.2

-

-

3.6

-

-

3.3

-

-

3.4

-

ns

tsu

set-up time

-

12.5

-

-

9.8

-

-

6.8

-

-

5.6

-

ns

th

hold time

-

3.4

-

-

3.3

-

-

3.1

-

-

2.8

-

ns

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