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ADS7863IDBQR Datasheet(PDF) 8 Page - Texas Instruments

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Part # ADS7863IDBQR
Description  Dual, 2MSPS, 12-Bit, 2 2 or 3 3 Channel, Simultaneous Sampling
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

ADS7863IDBQR Datasheet(HTML) 8 Page - Texas Instruments

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CLOCK
CONVST
10ns
Cyc e
l 1
Cyc e
l 2
A
B
C
10ns
5ns
5ns
ADS7863
SBAS383E – JUNE 2007 – REVISED JANUARY 2011
www.ti.com
TIMING CHARACTERISTICS (continued)
NOTE: All CONVST commands that occur more than 10ns before the rising edge of cycle ‘1’ of the external clock
(Region ‘A’) initiate a conversion on the rising edge of cycle ‘1’. All CONVST commands that occur 5ns after the rising
edge of cycle ‘1’ or 10ns before the rising edge of cycle 2 (Region ‘B’) initiate a conversion on the rising edge of cycle
‘2’. All CONVST commands that occur 5ns after the rising edge of cycle ‘2’ (Region ‘C’) initiate a conversion on the
rising edge of the next clock period.
The CONVST pin should never be switched from LOW to HIGH in the region 10ns prior to the rising edge of the
CLOCK and 5ns after the rising edge (gray areas). If CONVST is toggled in this gray area, the conversion could begin
on either the same rising edge of the CLOCK or the following edge.
Figure 2. CONVST Timing
TIMING REQUIREMENTS
(1)
Over recommended operating free-air temperature range at –40°C to +125°C, AVDD = 5V, and BVDD = 2.7V to 5V, unless
otherwise noted.
ADS7863
SYMBOL
PARAMETER
COMMENTS
MIN
MAX
UNIT
tCONV
Conversion time
fCLOCK = 32MHz
406.25
ns
tACQ
Acquisition time
fCLOCK = 32MHz
62.5
ns
fCLOCK
CLOCK frequency
See Figure 1
1
32
MHz
tCLOCK
CLOCK period
See Figure 1
31.25
1000
ns
tCKL
CLOCK low time
See Figure 1
9.4
ns
tCKH
CLOCK high time
See Figure 1
9.4
ns
t1
CONVST high time
See Figure 1
20
ns
t2
SDI setup time to CLOCK falling edge
See Figure 1
10
ns
t3
SDI hold time to CLOCK falling edge
See Figure 1
5
ns
t4
RD high setup time to CLOCK falling edge
See Figure 1
10
ns
t5
RD high hold time to CLOCK falling edge
See Figure 1
5
ns
t6
CONVST low time
See Figure 1
1
tCLOCK
t7
RD low time relative to CLOCK falling edge
See Figure 1
1
tCLOCK
t8
CS low to SDOx valid
See Figure 1
13
ns
See Figure 1,
4
11
ns
CLOCK rising edge to DATA valid delay
2.7V
≤ BVDD ≤ 3.6V
t9
(MIN = minimum hold time of current data;
See Figure 1,
MAX = maximum delay to new data valid)
3
9
ns
4.5V
≤ BVDD ≤ 5.5V
t10
CONVST rising edge to BUSY high delay(2)
See Figure 1
3
ns
t11
CLOCK rising edge to BUSY low delay
See Figure 1
3
ns
t12
CS low to RD high delay
See Figure 1
10
ns
(1)
All input signals are specified with tR = tF = 1.5ns (10% to 90% of BVDD) and timed from a voltage level of (VIL + VIH)/2.
(2)
Not applicable in auto-NAP power-down mode.
8
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Copyright © 2007–2011, Texas Instruments Incorporated
Product Folder Link(s): ADS7863


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