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TLK2711AIRCP Datasheet(PDF) 8 Page - Texas Instruments |
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TLK2711AIRCP Datasheet(HTML) 8 Page - Texas Instruments |
8 / 27 page TLK2711A SLLS908A – JULY 2008 – REVISED SEPTEMBER 2009.................................................................................................................................................. www.ti.com Figure 3. Transmission Latency 8-Bit/10-Bit Encoder All true serial interfaces require a method of encoding to insure minimum transition density so that the receiving PLL has a minimal number of transitions to stay locked on. The encoding scheme maintains the signal dc balance by keeping the number of ones and zeros the same. This provides good transition density for clock recovery and improves error checking. The TLK2711A uses the 8-bit/10-bit encoding algorithm that is used by fibre channel and gigabit ethernet. This is transparent to the user, as the TLK2711A internally encodes and decodes the data such that the user reads and writes actual 16-bit data. The 8-bit/10-bit encoder converts 8-bit wide data to a 10-bit wide encoded data character to improve its transmission characteristics. Since the TLK2711A is a 16-bit wide interface, the data is split into two 8-bit wide bytes for encoding. Each byte is fed into a separate encoder. The encoding is dependent upon two additional input signals, the TKMSB and TKLSB. Table 1. Transmit Data Controls TKLSB TKMSB 16 BIT PARALLEL INPUT 0 0 Valid data on TXD(0–7), Valid data TXD(8–15) 0 1 Valid data on TXD(0–7), K code on TXD(8–15)) 1 0 K code on TXD(0–7), Valid data on TXD(8–15) 1 1 K code on TXD(0–7), K code on TXD(8–15) PRBS Generator The TLK2711A has a built-in 27-1 PRBS (pseudorandom bit stream) function. When the PRBSEN terminal is forced high, the PRBS test is enabled. A PRBS is generated and fed into the 10-bit parallel-to-serial converter input register. Data from the normal input source is ignored during the PRBS mode. The PRBS pattern is then fed through the transmit circuitry as if it were normal data and sent out to the transmitter. The output can be sent to a BERT (bit error rate tester), the receiver of another TLK2711A, or looped back to the receive input. Since the PRBS is not really random but a predetermined sequence of ones and zeroes, the data can be captured and checked for errors by a BERT. Parallel-to-Serial The parallel-to-serial shift register takes in the 20-bit wide data word multiplexed from the two parallel 8-bit/10-bit encoders and converts it to a serial stream. The shift register is clocked on both the rising and falling edge of the internally generated bit clock, which is 10 times the TXCLK input frequency. The LSB (TXD0) is transmitted first. 8 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s) :TLK2711A |
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