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1

2

3

4

VCC

DIN+

DIN−

VCC

RGT PACKAGE

(TOP VIEW)

12

11

10

9

16

VCC

DOUT+

DOUT−

OUTPOL

15

14

13

5

6

7

8

P0019-02

EP

TLK4211EA

SLLS655 – NOVEMBER 2005

Figure 2. Pin Out of TLK4211EA in a 3 mm

× 3 mm 16-Pin QFN Package

TERMINAL FUNCTIONS

TERMINAL

TYPE

DESCRIPTION

NAME

NO.

VCC

1, 4 , 12

Supply

3.3-V

±10% supply voltage

DIN+

2

Analog in

Non-inverted data input. On-chip 100-

Ω terminated to DIN–

DIN–

3

Analog in

Inverted data input. On-chip 100-

Ω terminated to DIN+

NC

5, 7, 13

Not connected

DISABLE

6

CMOS in

Disables CML output stage when set to high level

GND

8, 16

Supply

Circuit ground.

Output data signal polarity select (internally pulled up):

OUTPOL

9

CMOS in

Setting to high-level or leaving pin open selects normal polarity.

Low-level selects inverted polarity.

DOUT–

10

CML out

Inverted data output. On-chip 50-

Ω back-terminated to VCC.

DOUT+

11

CML out

Non-inverted data output. On-chip 50-

Ω back-terminated to VCC.

Offset cancellation filter capacitor terminal 1. Connect an additional filter capacitor between this

COC1

14

Analog

pin and COC2 (pin 15). To disable the offset cancellation loop connect COC1 and COC2 (pins

14 and 15).

Offset cancellation filter capacitor terminal 2. Connect an additional filter capacitor between this

COC2

15

Analog

pin and COC1 (pin 14). To disable the offset cancellation loop connect COC1 and COC2 (pins

14 and 15).

EP

EP

Exposed die pad (EP) must be grounded.

3