TLV1117LV Series

SBVS160A

– MAY 2011 – REVISED SEPTEMBER 2011

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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

PRODUCT

TLV1117LVvv(A)yyyz

VV is the nominal output voltage (for example, 33 = 3.3 V).

YYY is the package designator.

Z is the package quantity. Use R for reel (2500 pieces), and T for tape (250 pieces).

(1)

For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the

device product folder at www.ti.com.

ABSOLUTE MAXIMUM RATINGS

(1)

VALUE

MIN

MAX

UNIT

–0.3

+6.0

V

Voltage

–0.3

+6.0

V

Current

Internally limited

Output short-circuit duration

Indefinite

Continuous total power

See Dissipation Ratings Table

dissipation

–55

+150

°C

Temperature

–55

+150

°C

Human body model (HBM) QSS 009-105 (JESD22-A114A)

2

kV

Electrostatic Discharge

Ratings

Charged device model (CDM) QSS 009-147 (JESD22-C101B.01)

500

V

(1)

Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods my affect device reliability.

THERMAL INFORMATION

TLV1117LV

DCY

UNITS

3 PINS

Junction-to-ambient thermal resistance

62.9

Junction-to-case (top) thermal resistance

47.2

Junction-to-board thermal resistance

12.0

°C/W

Junction-to-top characterization parameter

6.1

Junction-to-board characterization parameter

11.9

Junction-to-case (bottom) thermal resistance

N/A

(1)

For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953A.

DISSIPATION RATINGS

BOARD

PACKAGE

DCY

47.2

62.9

1.59 W

space

(1)

The JEDEC high K (2s2p) board used to derive these data was a 3-inch x 3-inch, multilayer board with 1-ounce internal power and

ground planes and 2-ounce copper traces on top and bottom of the board.

2

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