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APPLICATIONS

BUMPEDDIE

(BOTTOMVIEW)

SCLK

DV

DD

PD

DIN

LDAC

CS

FS

DGND

REFINAB

AV

DD

OUTA

OUTD

OUTB

OUTC

REFINCD

AGND

15

16

1

2

34

5

6

10

9

8

7

11

12

13

14

DESCRIPTION

TLV5614IYZ

SBAS401 – DECEMBER 2006

12-Bit, Quad Channel, 2.7V to 5.5V, DAC in

Bumped Die (Wafer Chip Scale) Package—Pb-Free/Green

• Battery-Powered Test Instruments

• Four 12-Bit D/A Converters

• Digital Offset and Gain Adjustment

• Programmable Settling Time of Either 3µs or

• Industrial Process Controls

9

µs Typ

• Machine and Motion Control Devices

• TMS320™DSP Family, (Q)SPI™, and

• Communications

Microwire™ Compatible Serial Interface

• Arbitrary Waveform Generation

• Internal Power-On Reset

• Low Power Consumption:

–

8mW, Slow Mode; 5V Supply

–

3.6mW, Slow Mode; 3V Supply

• Reference Input Buffer

• Voltage Output Range . . . 2x Reference Input

Voltage

• Monotonic Over Temperature

• Dual 2.7V to 5.5V Supply (Separate Digital and

Analog Supplies)

• Hardware Power-Down (10nA)

• Software Power-Down (10nA)

• Simultaneous Update

The TLV5614IYZ is a quadruple, 12-bit, voltage output digital-to-analog converter (DAC) with a flexible 4-wire

serial interface. The serial interface allows glueless interface to TMS320, SPI, QSPI, and Microwire serial ports.

The TLV5614IYZ is programmed with a 16-bit serial word comprised of a DAC address, individual DAC control

bits, and a 12-bit DAC value. The device has provision for two supplies: one digital supply for the serial interface

AGND). Each supply is independent of the other, and can be any value between 2.7V and 5.5V. The dual

supplies allow a typical application where the DAC is controlled via a microprocessor operating on a 3V supply

supplies can also be tied together.

The resistor string output voltage is buffered by a 2x gain rail-to-rail output buffer. The buffer features a

Class-AB output stage to improve stability and reduce settling time. A rail-to-rail output stage and a power-down

mode makes it ideal for single voltage, battery-based applications. The DAC settling time is programmable,

allowing the designer to optimize speed versus power dissipation. Settling time is chosen by the control bits

within the 16-bit serial input string. A high-impedance buffer is integrated on the REFINAB and REFINCD

terminals to reduce the need for a low source impedance drive to the terminal. REFINAB and REFINCD allow

DACs A and B to have a different reference voltage than DACs C and D.

The TLV5614IYZ is built with a CMOS process and is available in a 16-terminal bumped die (wafer chip scale)

package. It is characterized for operation from –40

°C to +85°C in a wire-bonded, small outline (SOIC) package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

TMS320 is a trademark of Texas Instruments, Inc.

SPI is a trademark of Motorola, Inc.

Microwire is a trademark of National Semiconductor Corporation.

MCS is a registered trademark of National Semiconductor Corporation.

All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Copyright © 2006, Texas Instruments Incorporated

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.