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TLV5619-EP Datasheet(PDF) 6 Page - Texas Instruments |
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TLV5619-EP Datasheet(HTML) 6 Page - Texas Instruments |
6 / 25 page TLV5619EP 2.7 V TO 5.5 V 12BIT PARALLEL DIGITALTOANALOG CONVERTER WITH POWER DOWN SGLS124A − JULY 2002 − REVISED DECEMBER 2003 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 operating characteristics over recommended operating free-air temperature range, supply voltages, and reference voltages (unless otherwise noted) analog output dynamic performance PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SR Slew rate CL = 100 pF, RL = 10 kΩ, Vref(REFIN) = 2.048 V, 1.024 V, 5-V Supply 8 12 V/ µs SR Slew rate RL = 10 kΩ, Code 32 to code 4095, Code 4095 to code 32, 1.024 V, VO from 10% to 90% 90% to 10% 3-V Supply 6 9 V/ µs ts Output settling time (full scale) To ±0.5 LSB, RL = 10 kΩ, CL = 100 pF, See Note 13 1 3 µs Glitch energy DIN = all 0s to all 1s 5 nV−s S/N Signal to noise fs = 480 kSPS, BW = 20 kHz, CL = 100 pF, fOUT = 1 kHz, RL = 10 kΩ TA = 25°C, See Note 14 5-V Supply 65 78 S/(N+D) Signal to noise + distortion fs = 480 kSPS, BW = 20 kHz, fOUT = 1 kHz, RL = 10 kΩ 5-V Supply 58 67 S/(N+D) Signal to noise + distortion BW = 20 kHz, CL = 100 pF, RL = 10 kΩ, TA = 25°C, See Note 14 3-V Supply 58 69 dB Total harmonic distortion fs = 480 kSPS, BW = 20 kHz, CL = 100 pF, fOUT = 1 kHz, RL = 10 kΩ, TA = 25°C, See Note 14 −68 −60 dB Spurious free dynamic range fs = 480 kSPS, BW = 20 kHz, CL = 100 pF, fOUT = 1 kHz, RL = 10 kΩ, TA = 25°C, See Note 14 60 72 NOTES: 13. Settling time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change of 0x020 to 0x3DF or 0x3DF to 0x020. Limits are ensured by design and characterization, but are not production tested. 14. 1 kHz sinewave generated by DAC, reference voltage = 1.024 V at 3 V and 2.048 V at 5 V. timing requirement digital inputs MIN NOM MAX UNIT tsu(CS-WE) Setup time, CS low before positive WE edge 13 ns tsu(D) Setup time, data ready before positive WE edge 9 ns th(D) Hold time, data held after positive WE edge 0 ns tsu(WE-LD) Setup time, positive WE edge before LDAC low 0 ns twh(WE) Pulse width, WE high 25 ns tw(LD) Pulse width, LDAC low 25 ns |
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