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P5CC012XU Datasheet(PDF) 5 Page - NXP Semiconductors |
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P5CC012XU Datasheet(HTML) 5 Page - NXP Semiconductors |
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5 / 15 page  P5CC008V1A_P5CC012V1A_FAM_SDS All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product short data sheet COMPANY PUBLIC Rev. 3 — 22 August 2012 195430 5 of 15 NXP Semiconductors P5CC008V1A and P5CC012V1A Secure contact PKI smart card controller Contact configuration and serial interface according to ISO/IEC 7816: GND, VCC, CLK, RST, I/O ISO/IEC 7816 UART supporting standard protocols T=0 and T=1 as well as high speed personalization up to 1 Mbit/s Support of major Public Key Cryptography (PKC) systems like RSA, Elgamel, DSS, Diffie-Hellman, Guillou-Quisquater, Fiat-Shamir and Elliptic Curves 8192 bits maximum key length for RSA with randomly chosen modulus 4096 bits maximum key length for calculation within RAM 32-bit operand input/output interface Boolean operations for acceleration of standard, symmetric cipher algorithms Externally or internally generated configurable CPU clock 1 MHz to 10 MHz operating external clock frequency range Internal clocking independent of externally applied frequency High speed 16-bit CRC engine according to ITU-T polynomial definition Low power Random Number Generator (RNG) in hardware, AIS-31 compliant 1.62 V to 5.5 V operating voltage range for Class C, B and A Optional extended Class B operation mode (2.2 V to 3.3 V targeted for battery supplied applications) 25 Cto+85 C ambient temperature Broad spectrum of delivery types Wafers Modules 2.2 Security features Enhanced security sensors Low and high clock frequency sensor Low and high temperature sensor Low and high supply voltage sensor Single Fault Injection (SFI) attack detection Light sensors (included integrated memory light sensor functionality) Electronic fuses for safeguarded mode control Active Shielding Unique ID for each die Clock input filter for protection against spikes Power-up / Power-down reset Optional programmable card disable feature Memory security (encryption and physical measures) for RAM, EEPROM and ROM Optional disabling of ROM read instructions by code executed in EEPROM Optional disabling of any code execution out of RAM EEPROM programming: No external clock Hardware sequencer controlled On-chip high voltage generation Enhanced error correction mechanism |
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