MAX5982B datasheet(4/17 Pages) MAXIM

Part #	MAX5982B

Description	IEEE 802.3af/at-Compliant, Powered Device Interface

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Manufacturer	MAXIM [Maxim Integrated Products]

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IEEE 802.3af/at-Compliant, Powered Device Interface

Controllers with Integrated 70W High-Power MOSFET

4 ______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(VIN = (VDD - VSS) = 48V, RDET = 24.9kω, RCLS = 615ω, and RSL = 60.4kω. RTN, WAD, PG, 2EC, WK, and ULP unconnected, all

voltages are referenced to VSS, unless otherwise noted. TA = TJ = -40NC to +85NC, unless otherwise noted. Typical values are at

TA = +25NC.) (Note 3)

Note 3: All devices are 100% production tested at TA = +25NC. Limits over temperature are guaranteed by design.

Note 4: The input offset current is illustrated in Figure 1.

Note 5: Effective differential input resistance is defined as the differential resistance between VDD and VSS. See Figure 1.

Note 6: Classification current is turned off whenever the device is in power mode.

Note 7: UVLO hysteresis is guaranteed by design, not production tested.

Note 8: A 20V glitch on input voltage, which takes VDD below VON shorter than or equal to tOFF_DLY does not cause the

MAX5982A/MAX5982B/MAX5982C to exit power-on mode.

Note 9: Maximum current limit during normal operation is guaranteed by design; not production tested.

Note 10: In power mode, current-limit foldback is used to reduce the power dissipation in the isolation MOSFET during an

overload condition across VDD and RTN.

Figure 1. Effective Differential Input Resistance/Offset Current

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

LED Current Programmable

Range

10

20

mA

LED Current with Grounded SL

VSL = 0V

20.5

24.5

28.5

mA

LED Current Frequency

fILED

Normal and ultra-low-power sleep modes

250

Hz

LED Current Duty Cycle

DILED

Normal and ultra-low-power sleep modes

25

%

VDD Current Amplitude

IVDD

Normal sleep mode, VLED = 3.5V

10

11

12.2

mA

Internal Current Duty Cycle

DIVDD

Normal and ultra-low-power sleep modes

75

%

Internal Current Enable Time

tMPS

Ultra-low-power sleep mode

80

84

88

ms

Internal Current Disable Time

tMPDO

Ultra-low-power sleep mode

220

228

236

ms

SL Delay Time

tSL

Time VSL must remain below the SL logic

threshold to enter sleep and ultra-low-

power modes (MAX5982A)

5.4

6.0

6.6

s

THERMAL SHUTDOWN

Thermal-Shutdown Threshold

TSD

TJ rising

+150

N

C

Thermal-Shutdown Hysteresis

TJ falling

30

N

C

IIN

IINi + 1

IINi

IOFFSET

dRi

1V

VINi

VINi + 1

IOFFSET = IINi -

VINi

dRi

dRi =

(VINi + 1 - VINi)

=

1V

(IINi + 1 - IINi) (IINi + 1 - IINi)

VIN

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