TM2EP64DPN, TM2EP64DJN, TM4EP64DPN, TM4EP64DJN

TM2EP72DPN, TM2EP72DJN, TM4EP72DPN, TM4EP72DJN

EXTENDEDDATAOUT DYNAMIC RAM MODULES

SMMS684A − AUGUST 1997 − REVISED FEBRUARY 1998

7

POST OFFICE BOX 655303

POST OFFICE BOX 1443

−0.5 V to 4.6 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage range on any pin (see Note 1)

− 0.5 V to 4.6 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Short-circuit output current

50 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Power dissipation: TM2EP64DxN

8 W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TM2EP72DxN

9 W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TM4EP64DxN

16 W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TM4EP72DxN

18 W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

0

°C to 70°C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

− 55

°C to 125°C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltage values are with respect to VSS.

recommended operating conditions

MIN

NOM

MAX

UNIT

VDD

Supply voltage

3

3.3

3.6

V

VSS

Supply voltage

0

V

VIH

High-level input voltage

2

VDD + 0.3

V

VIH −SPD

High-level input voltage for the SPD device

2

5.5

V

VIL

Low-level input voltage

− 0.3

0.8

V

TA

Ambient temperature

0

70

°C

capacitance over recommended ranges of supply voltage and ambient temperature, f = 1 MHz

(see Note 2)

PARAMETER

’2EP64DxN

’2EP72DxN

’4EP64DxN

’4EP72DxN

UNIT

PARAMETER

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

UNIT

Ci(A)

Input capacitance, A0 − A10

42

47

82

92

pF

Ci(OE)

Input capacitance, OEx

30

37

58

72

pF

Ci(CAS)

Input capacitance, CASx

9

16

16

30

pF

Ci(RAS)

Input capacitance, RASx

30

37

30

37

pF

Ci(W)

Input capacitance, WEx

30

37

38

37

pF

Co

Output capacitance

9

9

16

16

pF

Ci/o(SDA)

Input/output capacitance, SDA input

9

9

9

9

pF

Ci(SPD)

Input capacitance, SA0,SA1,SA2,SCL inputs

7

7

7

7

pF

NOTE 2: VDD = NOM supply voltage ± 10%, and the bias on pins under test is 0 V.