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TMS320LC203PZ Datasheet(PDF) 5 Page - Texas Instruments |
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TMS320LC203PZ Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 84 page  TMS320C203, TMS320C209, TMS320LC203 DIGITAL SIGNAL PROCESSORS SPRS025B – JUNE 1995 – REVISED AUGUST 1998 5 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C203 and TMS320LC203 Terminal Functions (Continued) TERMINAL TYPE† DESCRIPTION NAME NO. TYPE† DESCRIPTION OSCILLATOR, PLL, AND TIMER SIGNALS (CONTINUED) PLL5V 10 I PLL operating at 5 V. When the device is operating at 5 V, PLL5V should be tied high. When the device is operating at 3.3 V, PLL5V should be tied low. SERIAL PORT AND UART SIGNALS CLKX 87 I/O Transmit clock. CLKX is a clock signal for clocking data from the transmit shift register (XSR) to the DX data-transmit pin. The CLKX can be an input if the MCM bit in the synchronous serial-port control register (SSPCR) is set to 0. CLKX can also be driven by the device at one-half of the CLKOUT1 frequency when MCM = 1. If the serial port is not being used, CLKX goes into the high-impedance state when OFF is active low. Value at reset is as an input. CLKR 84 I/O Receive-clock input. External clock signal for clocking data from the DR (data-receive) pin into the serial-port receive shift register (RSR). CLKR must be present during serial-port transfers. If the serial port is not being used, CLKR can be sampled as an input by the IN0 bit of the SSPCR. FSR 85 I/O Frame synchronization pulse for receive input. The falling edge of the FSR pulse initiates the data-receive process, beginning the clocking of the RSR. FSR goes into the high-impedance state when OFF is active low. FSX 89 I/O Frame synchronization pulse for transmit input/ouput. The falling edge of the FSX pulse initiates the data-transmit process, beginning the clocking of the serial-port transmit shift register (XSR). Following reset, FSX is an input. FSX can be selected by software to be an output when the TXM bit in the SSPCR is set to 1. FSX goes into the high-impedance state when OFF is active low. DR 86 I Serial-data receive input. Serial data is received in the receive shift register (RSR) through the DR pin. DX 90 O Serial-port transmit output. Serial data is transmitted from the transmit shift register (XSR) through the DX pin. DX is in the high-impedance state when OFF is active low. TX 93 O Asynchronous transmit pin RX 95 I Asynchronous receive pin TEST SIGNALS TRST 79 I IEEE Standard 1149.1 (JTAG) test reset. TRST, when active high, gives the scan system control of the operations of the device. If TRST is not connected or driven low, the device operates in its functional mode, and the test signals are ignored. If the TRST pin is not driven, an external pulldown resistor must be used. TCK 78 I JTAG test clock. TCK is normally a free-running clock signal with a 50% duty cycle. The changes on the test-access port (TAP) input signals (TMS and TDI) are clocked into the TAP controller, instruction register, or selected test-data register on the rising edge of TCK. Changes at the TAP output signal (TDO) occur on the falling edge of TCK. TMS 81 I JTAG test-mode select. TMS is clocked into the TAP controller on the rising edge of TCK. TDI 80 I JTAG test-data input. TDI is clocked into the selected register (instruction or data) on a rising edge of TCK. TDO 82 O/Z JTAG test-data output. The contents of the selected register (instruction or data) are shifted out of TDO on the falling edge of TCK. TDO is in the high-impedance state except when the scanning of data is in progress. EMU0 76 I/O/Z Emulator pin 0. When TRST is driven low, EMU0 must be high for activation of the OFF condition. When TRST is driven high, EMU0 is used as an interrupt to or from the emulator system and is defined as an input/output through the JTAG scan. EMU1/OFF 77 I/O/Z Emulator pin 1. Emulator pin 1 disables all outputs. When TRST is driven high, EMU1/OFF is used as an interrupt to or from the emulator system and is defined as an input/output through the JTAG scan. When TRST is driven low, this pin is configured as OFF. EMU1/OFF, when active low, puts all output drivers in the high-impedance state. Note that OFF is used exclusively for testing and emulation purposes (not for multiprocessing applications). Therefore, for the OFF condition, the following apply: TRST = 0 EMU0 = 1 EMU/OFF = 0 † I = input, O = output, Z = high impedance, PWR = power, GND = ground |
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