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TMS470R1VF45AA Datasheet(PDF) 9 Page - Texas Instruments |
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TMS470R1VF45AA Datasheet(HTML) 9 Page - Texas Instruments |
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9 / 59 page  TMS470R1VF45AA 16/32-BIT RISC FLASH MICROCONTROLLER SPNS086A – AUGUST 2003 – REVISED NOVEMBER 2004 9 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443 Terminal Functions (Continued) † I = input, O = output, PWR = power, GND = ground, REF = reference voltage, NC = no connect ‡ All I/O pins, except RST, are configured as inputs while PORRST is low and immediately after PORRST goes high. § IPD = internal pulldown, IPU = internal pullup (all internal pullups and pulldowns are active on input pins, independent of the PORRST state.) TERMINAL TYPE†‡ INTERNAL PULLUP/ PULLDOWN§ DESCRIPTION NAME NO. MULTI-BUFFERED ANALOG-TO-DIGITAL CONVERTER (MibADC) (CONTINUED) ADIN[13] 112 3.3-V I MibADC analog input pins ADIN[14] 110 ADIN[15] 103 ADREFHI 116 3.3-V REF I MibADC module high-voltage reference input ADREFLO 117 GND REF I MibADC module low-voltage reference input VCCAD 118 3.3-V PWR MibADC analog supply voltage VSSAD 119 GND MibADC analog ground reference SERIAL PERIPHERAL INTERFACE 1 (SPI1) SPI1CLK 5 3.3-V I/O IPD SPI1 clock. SPI1CLK can be programmed as a GIO pin. SPI1ENA 1 SPI1 chip enable. SPI1ENA can be programmed as a GIO pin. SPI1SCS 2 SPI1 slave chip select. SPI1SCS can be programmed as a GIO pin. SPI1SIMO 3 SPI1 data stream. Slave in/master out. SPI1SIMO can be programmed as a GIO pin. SPI1SOMI 4 SPI1 data stream. Slave out/master in. SPI1SOMI can be programmed as a GIO pin. SERIAL PERIPHERAL INTERFACE 2 (SPI2) SPI2CLK 62 3.3-V I/O IPD SPI2 clock. SPI2CLK can be programmed as a GIO pin. SPI2ENA 65 SPI2 chip enable. SPI2ENA can be programmed as a GIO pin. SPI2SCS 66 SPI2 slave chip select. SPI2SCS can be programmed as a GIO pin. SPI2SIMO 63 SPI2 data stream. Slave in/master out. SPI2SIMO can be programmed as a GIO pin. SPI2SOMI 64 SPI2 data stream. Slave out/master in. SPI2SOMI can be programmed as a GIO pin. SERIAL PERIPHERAL INTERFACE 3 (SPI3) SPI3CLK 94 3.3-V I/O IPD SPI3 clock. SPI3CLK can be programmed as a GIO pin. SPI3ENA 98 SPI3 chip enable. SPI3ENA can be programmed as a GIO pin. SPI3SCS 97 SPI3 slave chip select. SPI3SCS can be programmed as a GIO pin. SPI3SIMO 96 SPI3 data stream. Slave in/master out. SPI3SIMO can be programmed as a GIO pin. SPI3SOMI 95 SP3 data stream. Slave out/master in. SPI3SOMI can be programmed as a GIO pin. ZERO-PIN PHASE-LOCKED LOOP (ZPLL) OSCIN 13 1.8-V I Crystal connection pin or external clock input OSCOUT 12 1.8-V O External crystal connection pin PLLDIS 73 3.3-V I IPD Enable/disable the ZPLL. The ZPLL can be bypassed and the oscillator becomes the system clock. If not in bypass mode, TI recommends that this pin be connected to ground or pulled down to ground by an external resistor. SERIAL COMMUNICATIONS INTERFACE 1 (SCI1) SCI1CLK 89 3.3-V I/O IPD SCI1 clock. SCI1CLK can be programmed as a GIO pin. SCI1RX 91 3.3-V I/O IPU SCI1 data receive. SCI1RX can be programmed as a GIO pin. SCI1TX 90 3.3-V I/O IPU SCI1 data transmit. SCI1TX can be programmed as a GIO pin. SERIAL COMMUNICATIONS INTERFACE 2 (SCI2) SCI2CLK 45 3.3-V I/O IPD SCI2 clock. SCI2CLK can be programmed as a GIO pin. SCI2RX 43 3.3-V I/O IPU SCI2 data receive. SCI2RX can be programmed as a GIO pin. SCI2TX 44 3.3-V I/O IPU SCI2 data transmit. SCI2TX can be programmed as a GIO pin. |
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