TMS470R1VF334

16/32-BIT RISC FLASH MICROCONTROLLER

SPNS081D – MARCH 2003 – REVISED AUGUST 2006

7

POST OFFICE BOX 1443

Terminal Functions

† I = input, O = output, PWR = power, GND = ground, REF = reference voltage, NC = no connect

‡ All I/O pins, except RST, are configured as inputs while PORRST is low and immediately after PORRST goes high.

§ IPD = internal pulldown, IPU = internal pullup (all internal pullups and pulldowns are active on input pins, independent of the PORRST state.)

TERMINAL

INTERNAL

PULLUP/

DESCRIPTION

NAME

VF334

HIGH-END TIMER (HET)

HET[0]

72

3.3-V I/O

IPD

The VF334 device has both the logic and registers for a full 32-I/O HET

implemented, even though not all 32 pins are available externally

Timer input capture or output compare. The HET[31:0] applicable pins can be

programmed as general-purpose input/output (GIO) pins.

HET pins [22, 20, 18, 16, 14, 12, 8, 7, 6, 4, 2, and 0]are high-resolution pins for

VF334.

HET[24] is a standard-resolution pin.

The high-resolution (HR) SHARE feature allows even HR pins to share the next

higher odd HR pin structures. This HR sharing is independent of whether or not

the odd pin is available externally. If an odd pin is available externally and shared,

then the odd pin can only be used as a general-purpose I/O. For more information

on HR SHARE, see the TMS470R1x High-End Timer Reference Guide (literature

number SPNU199).

HET[2]

77

HET[4]

78

HET[6]

79

HET[7]

80

HET[8]

45

HET[12]

15

HET[14]

14

HET[16]

13

HET[18]

39

HET[20]

38

HET[22]

37

HET[24]

27

STANDARD CAN CONTROLLER (SCC)

CANSRX

49

3.3-V I/O

SCC receive pin or GIO pin

CANSTX

50

3.3-V I/O

IPU

SCC transmit pin or GIO pin

CLASS II SERIAL INTERFACE (C2SIA)

C2SIaLPN

28

3.3-V I/O

IPD

C2SIa module loopback enable pin or GIO pin

C2SIaRX

30

3.3-V I/O

C2SIa module receive data input pin or GIO pin

C2SIaTX

29

3.3-V I/O

IPD

C2SIa module transmit data output pin or GIO pin

GENERAL-PURPOSE I/O (GIO)

GIOA[0]/INT0

23

3.3-V I

IPD

General-purpose input/output pins. GIOA[0]/INT[0] is an input-only pin.

GIOA[7:0]/INT[7:0] are interrupt-capable pins.

GIOA[1]/INT[1]/ECLK pin is multiplexed with the external clock-out function of the

external clock prescale (ECP) module.

GIOA[2]/INT[2] and GIOA[3]/INT[3]] pins are not applicable on the VF334 device.

GIOA[1]/INT1/

ECLK

24

3.3-V I/O

GIOA[4]/INT4

20

GIOA[5]/INT5

19

GIOA[6]/INT6

18

GIOA[7]/INT7

17

MULTI-BUFFERED ANALOG-TO-DIGITAL CONVERTER (MibADC)

ADEVT

56

3.3-V I/O

IPD

MibADC event input. ADEVT can be programmed as a GIO pin.

ADIN[0]

60

3.3-V I

MibADC analog input pins

The VF334 device has only 8 input channels but all S/W registers are capable.

ADIN[15,13, 11, 9, 7, 5, 3, and 1] pins are not applicable to the VF334 device.

ADIN[2]

59

ADIN[4]

58

ADIN[6]

57

ADIN[8]

64

ADIN[10]

62

ADIN[12]

63

ADIN[14]

61

65

3.3-V REF I

MibADC module high-voltage reference input

66

GND REF I

MibADC module low-voltage reference input

67

3.3-V

PWR

MibADC analog supply voltage

68

GND

MibADC analog ground reference