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TPS3808G30QDBVRQ1 Datasheet(PDF) 4 Page - Texas Instruments |
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TPS3808G30QDBVRQ1 Datasheet(HTML) 4 Page - Texas Instruments |
4 / 20 page RESET GND MR 6 5 4 V DD SENSE C T 1 2 3 DRV PACKAGE (TOP VIEW) RESET GND MR 1 2 3 6 5 4 DBV (SOT-23) PACKAGE (TOP VIEW) C T SENSE V DD Reset Logic Timer + − 90k V DD VDD GND 0.4 V V REF SENSE MR C T RESET R1 R 2 R 1 + R2 = 4 MW Reset Logic Timer + − 90k V DD VDD GND 0.4 V V REF SENSE MR C T RESET TPS3808-Q1 SBVS085H – JANUARY 2007 – REVISED JUNE 2012 www.ti.com FUNCTIONAL BLOCK DIAGRAMS Adjustable-Voltage Version Fixed-Voltage Versions PIN ASSIGNMENTS PIN FUNCTIONS PIN DESCRIPTION NAME NO. Reset. This is an open-drain output that is driven to a low impedance state when RESET is asserted (either the SENSE input is lower than the threshold voltage (VIT) or the MR pin is set to a logic low). RESET remains RESET 1 low (asserted) for the reset period after both SENSE is above VIT and MR is set to a logic high. A pullup resistor from 10 k Ω to 1 MΩ should be used on this pin, and allows the reset pin to attain voltages higher than VDD. GND 2 Ground MR 3 Manual reset. Driving this pin low asserts RESET. MR is internally tied to VDD by a 90-kΩ pullup resistor. Reset period programming. Connecting this pin to VDD through a 40-kΩ to 200-kΩ resistor or leaving it open CT 4 results in fixed delay times (see Electrical Characteristics). Connecting this pin to a ground referenced capacitor ≥ 100 pF gives a user-programmable delay time. Voltage sense. This pin is connected to the voltage to be monitored. If the voltage at this terminal drops below SENSE 5 the threshold voltage (VIT), RESET is asserted. VDD 6 Supply voltage. It is good analog design practice to place a 0.1- μF ceramic capacitor close to this pin. 4 Copyright © 2007–2012, Texas Instruments Incorporated |
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