ISLA214P12

11

FN7982.2

June 27, 2012

LVDS OUTPUTS

Differential Output Voltage (Note 11)

3mA Mode

612

Output Offset Voltage

3mA Mode

1120

1150

1200

mV

Output Rise Time

240

ps

Output Fall Time

240

ps

CMOS OUTPUTS

Voltage Output High

OVDD - 0.3 OVDD - 0.1

V

Voltage Output Low

0.1

0.3

V

Output Rise Time

1.8

ns

Output Fall Time

1.4

ns

NOTES:

10. The Tri-Level Inputs internal switching thresholds are approximately. 0.43V and 1.34V. It is advised to float the inputs, tie to ground or AVDD

depending on desired function.

11. The voltage is expressed in peak-to-peak differential swing. The peak-to-peak singled-ended swing is 1/2 of the differential swing.

PARAMETER

SYMBOL

CONDITIONS

MIN

(Note 5)

TYP

MAX

(Note 5) UNITS

Timing Diagrams

FIGURE 1A. LVDS DDR

CLKN

CLKP

INP

INN

CLKOUTN

CLKOUTP

D[12/10/8/6/4/2/0]N

D[12/10/8/6/4/2/0]P

LATENCY = L CYCLES

ODD

N-L

EVEN

N-L

ODD

N-L+1

EVEN

N-L+1

EVEN

N-1

ODD

N

EVEN

N