SW

VBST

EN

VO

VFB

GND

PGND

VO

4

6

9

10

11

1

2

7

12

VIN

SS

VIN

VREG5

EN

Logic

UV

OV

Protection

Logic

Ref

SS

UV

OV

UVLO

UVLO

Softstart

SS

REF

TSD

Ref

VREG5

5

PG

1mF

13

8

VCC

Ceramic

Capacitor

3

SGND

SGND

PGND

VCC

+20%

-10%

Ref

VREG5

Control logic

1 shot

XCON

-30%

OCP

SW

PGND

ZC

SW

PGND

14

VREG5

TPS54225

SLVSA15C

– OCTOBER 2009 – REVISED FEBRUARY 2011

www.ti.com

Functional Block Diagram

OVERVIEW

The TPS54225 is a 2-A synchronous step-down (buck) converter with two integrated N-channel MOSFETs. It

operates using D-CAP2

™ mode control. The fast transient response of D-CAP2™ control reduces the output

capacitance required to meet a specific level of performance. Proprietary internal circuitry allows the use of low

ESR output capacitors including ceramic and special polymer types.

DETAILED DESCRIPTION

PWM Operation

The main control loop of the TPS54225 is an adaptive on-time pulse width modulation (PWM) controller that

supports a proprietary D-CAP2

™ mode control. D-CAP2™ mode control combines constant on-time control with

an internal compensation circuit for pseudo-fixed frequency and low external component count configuration with

both low ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output.

At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after internal one

6

© 2009–2011, Texas Instruments Incorporated

Product Folder Link(s): TPS54225