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PERFORMANCE GRAPHS

−30

−15

0

30

45

60

100

1 k

10 k

100 k

1 M

−90

−45

0

45

90

180

f − Frequency − Hz

LOOP RESPONSE

Gain

Phase

15

135

50

60

70

80

90

100

0

1

2

3

4

5

Load Current − A

EFFICIENCY

vs

LOAD CURRENT

Efficiency at 700 kHz

1.7

1.75

1.8

1.85

1.9

0

1

2

3

4

5

OUTPUT VOLTAGE

vs

LOAD CURRENT

START-UP WAVEFORMS

Time − 2 ms/div

10 mV/div

400 ns/div

OUTPUT RIPPLE VOLTAGE

Time − 100

µs/div

LOAD TRANSIENT RESPONSE

Time − 10

µs/div

75

55

35

0

1

2

85

95

AMBIENT TEMPERATURE

vs

LOAD CURRENT

125

3

4

115

45

25

65

105

board conditions listed in the Dissipation Rating

Table section of this data sheet.

DETAILED DESCRIPTION

Under Voltage Lock Out (UVLO)

TPS54311-EP, TPS54312-EP,

TPS54313-EP, TPS54314-EP,

TPS54315-EP, TPS54316-EP

SGLS376A – FEBRUARY 2007 – REVISED MARCH 2007

Figure 12.

Figure 13.

Figure 14.

Figure 15.

Figure 16.

Figure 17.

Figure 18.

The TPS54311-16 incorporates an under voltage lockout circuit to keep the device disabled when the input

voltage (VIN) is insufficient. During power up, internal circuits are held inactive until VIN exceeds the nominal

UVLO threshold voltage of 2.95 V. Once the UVLO start threshold is reached, device start-up begins. The

device operates until VIN falls below the nominal UVLO stop threshold of 2.8 V. Hysteresis in the UVLO

comparator, and a 2.5-

µs rising and falling edge deglitch circuit reduce the likelihood of shutting the device down

due to noise on VIN.

10

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